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54ACTQ273L PDF预览

54ACTQ273L

更新时间: 2024-01-21 21:53:58
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
8页 180K
描述
Quiet Series Octal D Flip-Flop

54ACTQ273L 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DFP, FL20,.3Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.13
系列:ACTJESD-30 代码:R-GDFP-F20
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:85000000 Hz
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL20,.3封装形状:RECTANGULAR
封装形式:FLATPACK电源:5 V
Prop。Delay @ Nom-Sup:11 ns传播延迟(tpd):10 ns
认证状态:Not Qualified筛选级别:MIL-PRF-38535 Class V
座面最大高度:2.286 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn63Pb37)端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
总剂量:100k Rad(Si) V触发器类型:POSITIVE EDGE
宽度:6.731 mm最小 fmax:95 MHz
Base Number Matches:1

54ACTQ273L 数据手册

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August 1998  
54ACTQ273  
Quiet Series Octal D Flip-Flop  
performance. FACT Quiet Series features GTO output  
control and undershoot corrector in addition to a split ground  
bus for superior performance.  
General Description  
The ACTQ273 has eight edge-triggered D-type flip-flops with  
individual D inputs and Q outputs. The common buffered  
Clock (CP) and Master Reset (MR) input load and reset  
(clear) all flip-flops simultaneously.  
Features  
n ICC reduced by 50%  
The register is fully edge-triggered. The state of each D in-  
put, one setup time before the LOW-to-HIGH clock transi-  
tion, is transferred to the corresponding flip-flop’s Q output.  
n Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
n Improved latch-up immunity  
All outputs will be forced LOW independently of Clock or  
Data inputs by a LOW voltage level on the MR input. The de-  
vice is useful for applications where the true output only is re-  
quired and the Clock and Master Reset are common to all  
storage elements.  
n Buffered common clock and asynchronous master reset  
n Outputs source/sink 24 mA  
n Faster prop delays than the standard ’AC/’ACT273  
n 4 kV minimum ESD immunity  
n Standard Microcircuit Drawing (SMD)  
5962-89735  
The ACTQ utilizes NSC Quiet Series technology to guaran-  
tee quiet output switching and improved dynamic threshold  
Logic Symbols  
IEEE/IEC  
DS100240-1  
DS100240-2  
Pin Names  
Description  
D0–D7  
MR  
Data Inputs  
Master Reset  
CP  
Clock Pulse Input  
Data Outputs  
Q0–Q7  
GTO is a trademark of National Semiconductor Corporation.  
FACT® is a registered trademark of Fairchild Semiconductor Corporation.  
FACT Quiet Series is a trademark of Fairchild Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS100240  
www.national.com  

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