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54ACT74L PDF预览

54ACT74L

更新时间: 2024-01-31 15:12:26
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
8页 171K
描述
Dual D-Type Positive Edge-Triggered Flip-Flop

54ACT74L 技术参数

生命周期:ActiveReach Compliance Code:compliant
风险等级:5.73Is Samacsys:N
系列:ACTJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:85 Hz
最大I(ol):24 A位数:1
功能数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
Prop。Delay @ Nom-Sup:14 ns传播延迟(tpd):14 ns
筛选级别:MIL-STD-883B座面最大高度:1.905 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:8.89 mm最小 fmax:85 MHz
Base Number Matches:1

54ACT74L 数据手册

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August 1998  
54AC74 54ACT74  
Dual D-Type Positive Edge-Triggered Flip-Flop  
Asynchronous Inputs:  
General Description  
The ’AC/’ACT74 is a dual D-type flip-flop with Asynchronous  
LOW input to SD (Set) sets Q to HIGH level  
LOW input to CD (Clear) sets Q to LOW level  
Clear and Set are independent of clock  
Simultaneous LOW on CD and SD makes both Q and Q  
HIGH  
Clear and Set inputs and complementary (Q, Q) outputs. In-  
formation at the input is transferred to the outputs on the  
positive edge of the clock pulse. Clock triggering occurs at a  
voltage level of the clock pulse and is not directly related to  
the transition time of the positive-going pulse. After the Clock  
Pulse input threshold voltage has been passed, the Data in-  
put is locked out and information present will not be trans-  
ferred to the outputs until the next rising edge of the Clock  
Pulse input.  
Features  
n ICC reduced by 50%  
n Output source/sink 24 mA  
n ’ACT74 has TTL-compatible inputs  
n Standard Microcircuit Drawing (SMD)  
— ’AC74: 5962-88520  
— ’ACT74: 5962-87525  
Logic Symbols  
DS100266-2  
DS100266-1  
Pin Names  
D1, D2  
CP1, CP2  
D1, CD2  
D1, SD2  
Q1, Q1, Q2, Q2  
Description  
Data Inputs  
IEEE/IEC  
Clock Pulse Inputs  
Direct Clear Inputs  
Direct Set Inputs  
Outputs  
C
S
DS100266-3  
FACT® is a registered trademark of Fairchild Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS100266  
www.national.com  

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