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54ABT573J-QML PDF预览

54ABT573J-QML

更新时间: 2024-02-27 17:53:41
品牌 Logo 应用领域
美国国家半导体 - NSC 总线驱动器总线收发器锁存器逻辑集成电路信息通信管理
页数 文件大小 规格书
12页 407K
描述
Octal D-Type Latch with TRI-STATE Outputs

54ABT573J-QML 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DFP, FL20,.3Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.41其他特性:BROADSIDE VERSION OF 373
系列:ABTJESD-30 代码:R-GDFP-F20
JESD-609代码:e0逻辑集成电路类型:BUS DRIVER
最大I(ol):0.048 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装等效代码:FL20,.3
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:6.7 ns传播延迟(tpd):7.5 ns
认证状态:Not Qualified筛选级别:MIL-PRF-38535
座面最大高度:2.286 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.731 mm
Base Number Matches:1

54ABT573J-QML 数据手册

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July 1998  
54ABT573  
Octal D-Type Latch with TRI-STATE® Outputs  
n Functionally identical to ’ABT373  
n TRI-STATE outputs for bus interfacing  
n Output sink capability of 48 mA, source capability of  
24 mA  
n Output switching specified for both 50 pF and 250 pF  
loads  
General Description  
The ’ABT573 is an octal latch with buffered common Latch  
Enable (LE) and buffered common Output Enable (OE) in-  
puts.  
This device is functionally identical to the ’ABT373 but has  
different pinouts.  
n Guaranteed latchup protection  
n High impedance glitch-free bus loading during entire  
power up and power down  
n Nondestructive hot insertion capability  
n Standard Microcircuit Drawing (SMD) 5962-9321901  
Features  
n Inputs and outputs on opposite sides of package allow  
easy interface with microprocessors  
n Useful as input or output port for microprocessors  
Ordering Code  
Military  
Package  
Number  
Package Description  
54ABT573J-QML  
J20A  
20-Lead Ceramic Dual-In-Line  
20-Lead Cerpack  
54ABT573W-QML  
54ABT573E-QML  
W20A  
E20A  
20-Lead Ceramic Leadless Chip Carrier, Type C  
Connection Diagram  
Pin Assignment  
for LCC  
Pin Assignment  
for DIP and Cerpack  
DS100219-39  
Pin  
Description  
DS100219-1  
Names  
D0–D7  
Data Inputs  
LE  
Latch Enable Input (Active HIGH)  
TRI-STATE Output Enable Input  
(Active LOW)  
OE  
O0–O7  
TRI-STATE Latch Outputs  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS100219  
www.national.com  

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