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54ABT541E-QML PDF预览

54ABT541E-QML

更新时间: 2024-02-03 04:45:42
品牌 Logo 应用领域
美国国家半导体 - NSC 驱动器
页数 文件大小 规格书
10页 263K
描述
Octal Buffer/Line Driver with TRI-STATE Outputs

54ABT541E-QML 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DFP, FL20,.3Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.51Is Samacsys:N
其他特性:WITH DUAL OUTPUT ENABLE控制类型:ENABLE LOW
系列:ABTJESD-30 代码:R-GDFP-F20
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.048 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL20,.3封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:5.3 ns
传播延迟(tpd):5.3 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:2.286 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:BICMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.731 mmBase Number Matches:1

54ABT541E-QML 数据手册

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August 1998  
54ABT541  
Octal Buffer/Line Driver with TRI-STATE® Outputs  
n Guaranteed latchup protection  
n High impedance glitch free bus loading during entire  
power up and power down cycle  
n Nondestructive hot insertion capability  
n Flow-through pinout for ease of PC board layout  
n Disable time less than enable time to avoid bus  
contention  
General Description  
The ’ABT541 is an octal buffer and line driver with  
TRI-STATE outputs designed to be employed as a memory  
and address driver, clock driver, or bus-oriented transmitter/  
receiver. The ’ABT541 is similar to the ’ABT244 with broad-  
side pinout.  
n Standard Microcircuit Drawing (SMD) 5962-9471801  
Features  
n Non-inverting buffers  
n Output sink capability of 48 mA, source capability of  
24 mA  
Ordering Code  
Military  
Package  
Number  
J20A  
Package Description  
54ABT541J-QML  
20-Lead Ceramic Dual-In-Line  
20-Lead Cerpack  
54ABT541W-QML  
54ABT541E-QML  
W20A  
E20A  
20-Lead Ceramic Leadless Chip Carrier, Type C  
Connection Diagram  
Pin Names  
OE1, OE2  
I0–I7  
Description  
Output Enable Input (Active Low)  
Inputs  
Pin Assignment  
DIP and Cerpack  
O0–O7  
Outputs  
Truth Table  
Inputs  
OE2  
Outputs  
OE1  
L
I
ABT541  
L
X
H
L
H
X
X
L
H
Z
Z
L
H
X
L
DS100217-1  
=
=
=
=
H
L
X
Z
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
Pin Assignment  
LCC  
High Impedance  
DS100217-30  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS100217  
www.national.com  

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