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54ABT373W-QML PDF预览

54ABT373W-QML

更新时间: 2024-02-16 00:44:12
品牌 Logo 应用领域
美国国家半导体 - NSC 锁存器逻辑集成电路
页数 文件大小 规格书
14页 360K
描述
Octal Transparent Latch with TRI-STATE Outputs

54ABT373W-QML 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:DFP, FL20,.3Reach Compliance Code:unknown
风险等级:5.81JESD-30 代码:R-XDFP-F20
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:D LATCH最大I(ol):0.048 A
位数:8功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
封装主体材料:CERAMIC封装代码:DFP
封装等效代码:FL20,.3封装形状:RECTANGULAR
封装形式:FLATPACK电源:5 V
Prop。Delay @ Nom-Sup:7 ns认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B子类别:FF/Latches
标称供电电压 (Vsup):5 V表面贴装:YES
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

54ABT373W-QML 数据手册

 浏览型号54ABT373W-QML的Datasheet PDF文件第2页浏览型号54ABT373W-QML的Datasheet PDF文件第3页浏览型号54ABT373W-QML的Datasheet PDF文件第4页浏览型号54ABT373W-QML的Datasheet PDF文件第5页浏览型号54ABT373W-QML的Datasheet PDF文件第6页浏览型号54ABT373W-QML的Datasheet PDF文件第7页 
July 1998  
54ABT373  
Octal Transparent Latch with TRI-STATE® Outputs  
n Guaranteed multiple output switching specifications  
n Output switching specified for both 50 pF and 250 pF  
loads  
n Guaranteed simultaneous switching, noise level and  
dynamic threshold performance  
n Guaranteed latchup protection  
n High impedance glitch free bus loading during entire  
power up and power down  
General Description  
The ’ABT373 consists of eight latches with TRI-STATE out-  
puts for bus organized system applications. The flip-flops ap-  
pear transparent to the data when Latch Enable (LE) is  
HIGH. When LE is LOW, the data that meets the setup times  
is latched. Data appears on the bus when the Output Enable  
(OE) is LOW. When OE is HIGH the bus output is in the high  
impedance state.  
n Nondestructive hot insertion capability  
n Standard Microcircuit Drawing (SMD) 5962-9321801  
Features  
n TRI-STATE outputs for bus interfacing  
n Output sink capability of 48 mA, source capability of  
24 mA  
Ordering Code  
Military  
54ABT373J-QML  
54ABT373W-QML  
54ABT373E-QML  
Package Number  
J20A  
Package Description  
20-Lead Ceramic Dual-In-Line  
W20A  
20-Lead Cerpack  
E20A  
20-Lead Ceramic Leadless Chip Carrier, Type C  
Connection Diagrams  
Pin Assignment  
for DIP and Flatpak  
Pin Assignment  
for LCC  
DS100206-2  
DS100206-1  
Pin Names  
Description  
Data Inputs  
D0–D7  
LE  
Latch Enable Input  
(Active HIGH)  
Output Enable Input  
(Active LOW)  
OE  
O0–O7  
TRI-STATE Latch  
Outputs  
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 1998 National Semiconductor Corporation  
DS100206  
www.national.com  

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