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5495A

更新时间： 2024-02-04 00:59:04

品牌	Logo	应用领域
美国国家半导体 - NSC		移位寄存器
页数	文件大小	规格书
6页	107K
描述
4-Bit Parallel Access Shift Registers

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5495A 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
逻辑集成电路类型：	PARALLEL IN PARALLEL OUT

5495A 数据手册

June 1989

5495A/DM7495

4-Bit Parallel Access Shift Registers

General Description

These 4-bit registers feature parallel and serial inputs, paral-

lel outputs, mode control, and two clock inputs. The regis-

ters have three modes of operation.

mode control is high by connecting the output of each flip-

flop to the parallel input of the previous flip-flop (Q to input

C, etc.) and serial data is entered at input D. The clock input

may be applied simultaneously to clock 1 and clock 2 if both

modes can be clocked from the same source.

Parallel (broadside) load

Shift right (the direction Q toward Q )

Shift left (the direction Q toward Q )

Changes at the mode control input should normally be

made while both clock inputs are low; however, conditions

described in the last three lines of the truth table will also

ensure that register contents are protected.

Parallel loading is accomplished by applying the four bits of

data and taking the mode control input high. The data is

loaded into the associated flip-flops and appears at the out-

puts after the high-to-low transition of the clock-2 input. Dur-

ing loading, the entry of serial data is inhibited.

Features

Typical maximum clock frequency 36 MHz

Shift right is accomplished on the high-to-low transition of

clock 1 when the mode control is low; shift left is accom-

plished on the high-to-low transition of clock 2 when the

Typical power dissipation 250 mW

Connection Diagram

Dual-In-Line Package

TL/F/6534–1

Order Number 5495ADMQB, 5495AFMQB or DM7495N

See NS Package Number J14A, N14A or W14B

1995 National Semiconductor Corporation

TL/F/6534

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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