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5476DMQB PDF预览

5476DMQB

更新时间: 2024-01-26 10:30:37
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
4页 111K
描述
Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs

5476DMQB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DFP包装说明:DFP, FL16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.32
系列:TTL/H/LJESD-30 代码:R-GDFP-F16
JESD-609代码:e0长度:9.6645 mm
逻辑集成电路类型:J-K FLIP-FLOP最大频率@ Nom-Sup:15000000 Hz
最大I(ol):0.016 A位数:2
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装等效代码:FL16,.3
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):34 mA传播延迟(tpd):40 ns
认证状态:Not Qualified筛选级别:MIL-STD-883 Class B
座面最大高度:2.032 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:6.604 mm最小 fmax:15 MHz
Base Number Matches:1

5476DMQB 数据手册

 浏览型号5476DMQB的Datasheet PDF文件第2页浏览型号5476DMQB的Datasheet PDF文件第3页浏览型号5476DMQB的Datasheet PDF文件第4页 
June 1989  
5476/DM5476/DM7476  
Dual Master-Slave J-K Flip-Flops with Clear,  
Preset, and Complementary Outputs  
General Description  
This device contains two independent positive pulse trig-  
gered J-K flip-flops with complementary outputs. The J and  
K data is processed by the flip-flop after a complete clock  
pulse. While the clock is low the slave is isolated from the  
master. On the positive transition of the clock, the data from  
the J and K inputs is transferred to the master. While the  
clock is high the J and K inputs are disabled. On the nega-  
tive transition of the clock, the data from the master is trans-  
ferred to the slave. The logic state of J and K inputs must  
not be allowed to change while the clock is high. The data is  
transfered to the outputs on the falling edge of the clock  
pulse. A low logic level on the preset or clear inputs will set  
or reset the outputs regardless of the logic levels of the  
other inputs.  
Features  
Y
Alternate Military/Aerospace device (5476) is available.  
Contact a National Semiconductor Sales Office/Distrib-  
utor for specifications.  
Connection Diagram  
Function Table  
Dual-In-Line Package  
Inputs  
CLK  
Outputs  
PR  
CLR  
J
K
Q
Q
L
H
L
H
L
X
X
X
X
L
X
X
X
L
H
L
L
H
X
L
X
H*  
H*  
Q
0
H
H
H
H
H
H
H
H
É
É
É
É
Q
0
H
L
L
H
L
H
H
L
H
H
Toggle  
e
e
e
H
L
High Logic Level  
Low Logic Level  
X
Either Low or High Logic Level  
e
É
Positive pulse data. The J and K inputs must be held constant while  
the clock is high. Data is transfered to the outputs on the falling edge of the  
clock pulse.  
e
and/or clear inputs return to their inactive (high) level.  
*
This configuration is nonstable; that is, it will not persist when the preset  
TL/F/6528–1  
Order Number 5476DMQB, 5476FMQB,  
DM5476J, DM5476W or DM7476N  
e
tablished.  
Q
0
The output logic level before the indicated input conditions were es-  
See NS Package Number J16A, N16E or W16A  
e
each complete active high level clock pulse.  
Toggle  
Each output changes to the complement of its previous level on  
C
1995 National Semiconductor Corporation  
TL/F/6528  
RRD-B30M105/Printed in U. S. A.  

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