August 1998
100351
Low Power Hex D Flip-Flop
General Description
Features
n 40% power reduction of the 100151
n 2000V ESD protection
The 100351 contains six D-type edge-triggered, master/
slave flip-flops with true and complement outputs, a pair of
common Clock inputs (CPa and CPb) and common Master
Reset (MR) input. Data enters a master when both CPa and
CPb are LOW and transfers to the slave when CPa and CPb
(or both) go HIGH. The MR input overrides all other inputs
and makes the Q outputs LOW. All inputs have 50 kΩ
pull-down resistors.
n Pin/function compatible with 100151
n Voltage compensated operating range:
−4.2V to −5.7V
n Standard Microcircuit Drawing
(SMD) 5962-9457901
Logic Symbol
Pin Names
D0–D5
Description
Data Inputs
CPa, CPb
MR
Common Clock Inputs
Asynchronous Master Reset Input
Data Outputs
Q0–Q5
Q0–Q5
Complementary Data Outputs
DS100318-11
© 1998 National Semiconductor Corporation
DS100318
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