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100331F PDF预览

100331F

更新时间: 2024-02-19 06:11:44
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
8页 153K
描述
Low Power Triple D Flip-Flop

100331F 技术参数

生命周期:Contact Manufacturer包装说明:QFF,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.59Is Samacsys:N
系列:100KJESD-30 代码:S-GQFP-F24
长度:9.398 mm逻辑集成电路类型:D FLIP-FLOP
位数:1功能数量:3
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:QFF封装形状:SQUARE
封装形式:FLATPACK传播延迟(tpd):2.4 ns
筛选级别:MIL-PRF-38535 Class V座面最大高度:2.159 mm
表面贴装:YES技术:ECL
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:QUAD
触发器类型:POSITIVE EDGE宽度:9.398 mm
最小 fmax:400 MHzBase Number Matches:1

100331F 数据手册

 浏览型号100331F的Datasheet PDF文件第2页浏览型号100331F的Datasheet PDF文件第3页浏览型号100331F的Datasheet PDF文件第4页浏览型号100331F的Datasheet PDF文件第5页浏览型号100331F的Datasheet PDF文件第6页浏览型号100331F的Datasheet PDF文件第7页 
August 1998  
100331  
Low Power Triple D Flip-Flop  
General Description  
Features  
n 35% power reduction of the 100131  
n 2000V ESD protection  
The 100331 contains three D-type, edge-triggered master/  
slave flip-flops with true and complement outputs, a Com-  
mon Clock (CPC), and Master Set (MS) and Master Reset  
(MR) inputs. Each flip-flop has individual Clock (CPn), Direct  
Set (SDn) and Direct Clear (CDn) inputs. Data enters a mas-  
ter when both CPn and CPC are LOW and transfers to a  
slave when CPn or CPC (or both) go HIGH. The Master Set,  
Master Reset and individual CDn and SDn inputs override  
the Clock inputs. All inputs have 50 kpull-down resistors.  
n Pin/function compatible with 100131  
=
n Voltage compensated operating range −4.2V to −5.7V  
n Available to industrial grade temperature range  
n Available to Standard Microcircuit Drawing (SMD)  
5962-9153601  
Logic Symbol  
Pin Names  
CP0–CP2  
CPC  
Description  
Individual Clock Inputs  
Common Clock Input  
Data Inputs  
D0–D2  
CD0–CD2  
SDn  
Individual Direct Clear Inputs  
Individual Direct Set Inputs  
Master Reset Input  
MR  
MS  
Master Set Input  
Q0-Q2  
Q0–Q2  
Data Outputs  
Complementary Data Outputs  
DS100300-1  
Connection Diagrams  
24-Pin DIP  
24-Pin Quad Cerpak  
DS100300-3  
DS100300-2  
© 1998 National Semiconductor Corporation  
DS100300  
www.national.com  

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