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UPD30181AYF1-131-GA3-A PDF预览

UPD30181AYF1-131-GA3-A

更新时间: 2024-01-09 15:04:20
品牌 Logo 应用领域
日电电子 - NEC 外围集成电路微处理器
页数 文件大小 规格书
72页 560K
描述
64-/32-BIT MICROPROCESSOR

UPD30181AYF1-131-GA3-A 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
针数:240Reach Compliance Code:compliant
风险等级:5.82Is Samacsys:N
位大小:32JESD-30 代码:S-PBGA-B240
JESD-609代码:e1湿度敏感等级:4
端子数量:240最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA240,18X18,40
封装形状:SQUARE封装形式:GRID ARRAY
电源:2.5,3.3 V认证状态:Not Qualified
速度:131 MHz子类别:Microprocessors
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOMuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

UPD30181AYF1-131-GA3-A 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
µPD30181A, 30181AY  
VR4181ATM  
64-/32-BIT MICROPROCESSOR  
DESCRIPTION  
The µPD30181A and 30181AY (VR4181A), which are high-performance 64-/32-bit microprocessors employing the  
RISC (reduced instruction set computer) architecture developed by MIPSTM, are products in the VR SeriesTM of  
microprocessors manufactured by NEC.  
The VR4181A includes as its CPU the VR4120™ core, an ultra-low-power-consumption core featuring cache  
memory, a high-speed product-sum operation unit, and a memory management unit. Other on-chip components  
include an LCD controller, CompactFlash controller, USB host/function controller, DMA controller, SDRAM controller,  
PWM controller, AC97/I2S audio interface, full-duplex asynchronous serial interface, IrDA interface, I2C serial  
interface, keyboard interface, touch panel interface, real-time clock, A/D converter, D/A converter, and other  
controllers and interfaces required for battery-driven mobile information devices, fixed compact information devices,  
car navigation systems, and compact embedded devices.  
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before  
designing.  
VR4181A Hardware User’s Manual (U16049E)  
VR4100 SeriesTM Architecture User’s Manual (U15509E)  
FEATURES  
{ VR4120 core (64-bit RISC core) on chip as CPU  
{ Pipeline clock: 131 MHz  
{ UMA type LCD controller (supports STN and TFT  
panels)  
{ Conforms to MIPS III (except for FPU, LL and SC { ExCA register-compatible CompactFlash interface (2  
instructions) and MIPS16 instruction sets slots)  
{ Supports MACC and DMACC high-speed product-sum { USB host controller (Rev1.1, OHCI Rev1.0)  
operation instructions  
controller  
{ On-chip cache memory  
{ USB function (Rev1.1) controller  
Capacity includes 8 KB instruction cache and 8 KB { AC97 and I2S audio interfaces (1 channel each)  
data cache  
{ Clocked serial interface (1 channel)  
{ NS16550-compatible serial interface (3 channels)  
{ IrDA (SIR) interface (1 channel)  
{ Employs a writeback cache  
{ Physical addresses: 32 bits  
Virtual addresses: 40 bits  
{ On-chip 32 double-entry TLB  
{ I2C bus interfaces (2 channels, µPD30181AY only)  
{ PWM controller (3 channels)  
{ Effective power management using four modes: { DMA controller supporting chain mode (4 channels)  
Fullspeed, Standby, Suspend, and Hibernate { Keyboard scan interface (supports 8 × 12 key matrix)  
{ Employs a high-performance internal system bus (T- { X-Y coordinate auto scan touch panel interface  
bus) { On-chip A/D converter and D/A converter  
{ DRAM controller supporting 64 Mb, 128 Mb, and 256 { On-chip watchdog timer unit  
Mb SDRAMs  
{ RTC unit (total of 3 timer and counter channels)  
{ External system bus interface supporting ROM, page { On-chip PLL and clock generators  
ROM, flash memory, SRAM, ISA devices, IDE (ATA) { Power supplies: 2.5 V for core, 3.3 V for I/O block  
devices, and SyncFlash™ memory  
{ Package: 240-pin plastic FBGA  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
Document No. U16277EJ1V0DS00 (1st edition)  
Date Published October 2002 N CP(K)  
Printed in Japan  
The mark  
shows major revised points.  
2002  
©
1997  
©

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