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MT8920BS PDF预览

MT8920BS

更新时间: 2024-02-28 12:59:00
品牌 Logo 应用领域
MITEL 光电二极管
页数 文件大小 规格书
29页 217K
描述
ISO-CMOS ST-BUS⑩ FAMILY ST-BUS Parallel Access Circuit

MT8920BS 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
针数:28Reach Compliance Code:unknown
HTS代码:8542.31.00.01风险等级:5.8
Is Samacsys:NJESD-30 代码:R-PDSO-G28
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP28,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:5 V认证状态:Not Qualified
子类别:Serial IO/Communication Controllers标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

MT8920BS 数据手册

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ISO-CMOS ST-BUS FAMILY MT8920B  
ST-BUS Parallel Access Circuit  
ISSUE 7  
March 1997  
Features  
High speed parallel access to the serial ST-BUS  
Ordering Information  
Parallel bus optimized for 68000 µP (mode 1)  
Fast dual-port RAM access (mode 2)  
Access time: 120 nsec  
MT8920BE  
28 Pin Plastic DIP  
MT8920BP  
MT8920BS  
28 Pin Plastic J-Lead  
28 Pin SOIC  
Parallel bus controller (mode 3) - no external  
controller required  
-40°C to 85°C  
Flexible interrupt capabilities - two  
independent/programmable interrupt sources  
with auto-vectoring  
Description  
Selectable 24 and 32 channel operation  
Programmable loop-around modes  
Low power CMOS technology  
The ST-BUS Parallel Access Circuit (STPA) provides  
a simple interface between Mitel’s ST-BUS and  
parallel system environments.  
Applications  
Parallel control/data access to T1/CEPT digital  
trunk interfaces  
Digital signal processor interface to ST-BUS  
Computer to Digital PABX link  
Voice store and forward systems  
Interprocessor communications  
Tx0  
Dual Port Ram  
32 X 8  
Parallel-  
D7-D0  
to-serial  
STo0  
STi0  
Converter  
A4-A0  
Rx0  
Dual Port Ram  
32 X 8  
Serial-to-  
Parallel  
CS  
Converter  
DS, OE  
Parallel  
Port  
R/W, WE  
Interface  
Tx1  
Dual Port Ram  
32 X 8  
Parallel-  
to-Serial  
Converter  
DTACK,  
BUSY, DCS  
STo1  
Interrupt  
Registers  
IRQ, 24/32  
Comp/  
MUX  
Control  
Registers  
IACK, MS1  
A5, STCH  
MMS  
F0i  
C4i  
Address  
Generator  
V
V
DD  
SS  
Figure 1 - Functional Block Diagram  
3-3  

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