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VSC8145XVQ-04 PDF预览

VSC8145XVQ-04

更新时间： 2024-02-06 05:28:24
品牌 Logo 应用领域
美高森美 - MICROSEMI ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
44页 497K
描述
ATM/SONET/SDH Transceiver, CMOS, PBGA156,

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VSC8145XVQ-04 技术参数

是否Rohs认证： 符合生命周期：Obsolete
包装说明：BGA, BGA156,16X16,50Reach Compliance Code：compliant
风险等级：5.82JESD-30 代码：S-PBGA-B156
端子数量：156最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA156,16X16,50
封装形状：SQUARE封装形式：GRID ARRAY
电源：2.5 V认证状态：Not Qualified
子类别：ATM/SONET/SDH ICs最大压摆率：425 mA
标称供电电压：2.5 V表面贴装：YES
技术：CMOS电信集成电路类型：ATM/SONET/SDH TRANSCEIVER
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
Base Number Matches：1

VSC8145XVQ-04 数据手册

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VSC8145-03 and VSC8145-04  
Datasheet  
Extended Multirate 4:1 SONET/SDH Transceiver with Integrated CRU/CMU  
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High-speed clock output power-down option  
Low-speed 4-bit LVDS I/O  
FEATURES  
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Integrated clock and data recovery unit  
LOS detect with automatic Lock to Reference  
Low-speed bit-order swap (MSB/LSB)  
Onboard FIFO with automatic reset function  
Equipment, Facility, and Split Loopback modes  
Rx/Tx internal Loop Timing mode  
Single 2.5 V power supply  
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Extended multirate support for:  
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STS-3/STM-1, STS-12/STM-4, STS-48/STM-16,  
with and without FEC  
•
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Gigabit Ethernet (1.25 Gbps and 2.50 Gbps)  
Fibre Channel (1.0625 Gbps and 2.125 Gbps)  
Fast Ethernet  
FDDI  
800 mW typical power consumption  
0.18 μm CMOS technology  
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Selectable CRU and CMU Bypass mode  
Complies with Telcordia and ITU-T jitter  
specifications  
GENERAL DESCRIPTION  
The VSC8145 device is a extended multirate transceiver with an integrated clock recovery unit (CRU) and a clock  
multiplier unit (CMU) designed for use in SONET/SDH systems operating at STS-3/STM-1, STS-12/STM-4,  
STS-48/STM-16 with Forward Error Correction (FEC), Gigabit Ethernet (GbE), Fibre Channel (FC), and various  
other data rates.  
This datasheet documents the VSC8145-03 and VSC8145-04 variants of the VSC8145 device. For information about  
differences between these variants and the VSC8145-01 and VSC8145-02 variants, see “Electrical Specifications,”  
page 23.  
The integrated CRU phase locked loop (PLL) recovers the high-speed clock from the input data. The integrated CMU  
PLL multiplies a low-speed reference clock to provide the high-speed serial line clock for internal logic and output  
retiming. The parallel 4-bit LVDS interface incorporates an onboard FIFO, eliminating loop timing issues. Facility,  
Equipment, and Split Loopback modes are supported by the VSC8145 device.  
Two selectable, externally-supplied reference clock inputs (REFCLK[0:1]) support the CRU PLL and CMU PLL  
operations by maintaining a lock condition when the high-speed data is missing at the input. The CRU and CMU can  
use the same reference clock input or can use separate inputs when the receive data and transmit data are not at the  
same rate. Two reference clock selector inputs, CRURS for the CRU, and CMURS for the CMU, allow selection  
between the two REFCLK inputs.  
A Loss of Lock (LOL) status signal indicates a loss of lock of the PLL. The Loss of Signal (LOS) status signal  
indicates the occurrence of an all zeros or all ones pattern. During a LOS condition, an all zeros data pattern is  
generated, along with a SONET-quality clock (for SONET rates only).  
VMDS-10163 Revision 4.0  
August 1, 2006  
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012  
Tel: (800) VITESSE • FAX: (805) 987-5896 • E-mail: prodinfo@vitesse.com  
Internet: www.vitesse.com  
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