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SY100EL15 PDF预览

SY100EL15

更新时间: 2024-01-28 18:53:49
品牌 Logo 应用领域
麦瑞 - MICREL 时钟
页数 文件大小 规格书
4页 65K
描述
1:4 CLOCK DISTRIBUTION

SY100EL15 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.150 INCH, SOIC-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.2
Is Samacsys:N系列:100EL
输入调节:DIFFERENTIAL MUXJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.93 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:16实输出次数:4
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:-4.2/-5.5 VProp。Delay @ Nom-Sup:0.75 ns
传播延迟(tpd):0.72 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1.73 mm
子类别:Clock Drivers表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.94 mm
Base Number Matches:1

SY100EL15 数据手册

 浏览型号SY100EL15的Datasheet PDF文件第2页浏览型号SY100EL15的Datasheet PDF文件第3页浏览型号SY100EL15的Datasheet PDF文件第4页 
Precision Edge™  
SY10EL15  
1:4 CLOCK  
DISTRIBUTION  
SY100EL15  
FINAL  
FEATURES  
50ps output-to-output skew  
Synchronous enable/disable  
Multiplexed clock input  
Precision Edge™  
DESCRIPTION  
75Kinternal input pull-down resistors  
Available in 16-pin SOIC package  
The SY10/100EL15 are low skew 1:4 clock distribution  
chips designed explicitly for low skew clock distribution  
applications. The device can be driven by either a  
differential or single-ended ECL or, if positive power  
supplies are used, PECL input signal. If a single-ended  
input is to be used the VBB output should be connected  
to the CLK input and bypassed to VCC via a 0.01µF  
capacitor. The VBB output is designed to act as the  
switching reference for the input of the EL15 under single-  
ended input conditions, as a result this pin can only  
source/sink up to 0.5mA of current.  
PIN CONFIGURATION/BLOCK DIAGRAM  
CLK CLK  
13 12  
VBB  
V
CC EN SCLK  
VEE  
SEL  
10  
16 15 14  
11  
9
1
0
The EL15 features a multiplexed clock input to allow  
for the distribution of a lower speed scan or test clock  
along with the high speed system clock. When LOW (or  
left open and pulled LOW by the input pull-down resistor)  
the SEL pin will select the differential clock input.  
D
Q
The common enable (EN) is synchronous so that the  
outputs will only be enabled/disabled when they are  
already in the LOW state. This avoids any chance of  
generating a runt clock pulse when the device is enabled/  
disabled as can happen with an asynchronous control.  
The internal flip flop is clocked on the falling edge of the  
input clock, therefore all associated specification limits  
are referenced to the negative edge of the clock input.  
3
4
5
6
7
2
8
1
Q
0
Q0  
Q
1
Q
1
Q
2
Q3  
Q
2
SOIC  
TOP VIEW  
PIN NAMES  
TRUTH TABLE  
Pin  
CLK  
SCLK  
EN  
Function  
CLK  
L
SCLK  
SEL  
L
EN  
L
Q
L
Differential Clock Inputs  
Synchronous Clock Input  
Synchronous Enable  
Clock Select Input  
X
X
L
H
L
L
H
L
X
H
L
SEL  
VBB  
X
H
X
H
L
H
L*  
Reference Output  
X
X
H
Q0-3  
Differential Clock Outputs  
* On next negative transition of CLK or SCLK  
Precision Edge is a trademark of Micrel, Inc.  
Rev.: G  
Amendment:/0  
Issue Date: February 2003  
1

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