19-1417; Rev 0; 12/98
MAX3 6 9 3 Eva lu a t io n Kit
Evluates:MAX693
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX3693 evaluation kit (EV kit) is an assembled,
surface-mount demonstration board that provides easy
evaluation of the MAX3693 622Mbps serializer with
clock synthesis and LVDS inputs.
♦ Single +3.3V Supply
♦ Selectable Clock-Reference Frequencies
(155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz)
♦ Fully Assembled and Tested Surface-Mount
Co m p o n e n t Lis t
Board
DESIGNATION QTY
DESCRIPTION
C4–C9, C11,
14
0.1µF, 10%, 25V min ceramic
capacitors
Ord e rin g In fo rm a t io n
C12, C16–C21
1µF, 10%, 10V min ceramic
capacitors X7R type
C13, C22
C14
2
1
1
PART
TEMP. RANGE
IC PACKAGE
MAX3693EVKIT
-40°C to +85°C
32 TQFP
1µF, 10%, 25V min ceramic capacitor
33µF, ±10%, 10V min tantalum
capacitor AVX TAJD336K010
C15
De t a ile d De s c rip t io n
56nH inductors
Coilcraft 0805CS-560XKBC
L1–L5
1
0
The MAX3693 EV kit s imp lifie s e va lua tion of the
MAX3693. The EV kit operates from a single +3.3V supply
and includes all the external components necessary to
interface with LVDS inputs and 3.3V PECL outputs.
R1, R2, R11,
C1–C3, C10,
JU1, JU2, JU4,
JU11–JU15
Not installed
The LVDS inp uts (PD_+ , PD_-, PCLKI+ , PCLKI-,
RCLK+, RCLK-) are internally terminated with 100Ω dif-
ferential input resistance, and therefore do not require
external termination. Ensure that LVDS devices driving
these inputs are not redundantly terminated. The LVDS
outputs (PCLKO+, PCLKO-) require a differential termi-
nation with a 100Ω resistor between complementary
outputs.
R3, R4
R5, R6
R7, R8
R9, R10
R12
2
2
2
2
1
27Ω, 5% resistors
220Ω, 5% resistors
130Ω, 5% resistors
24Ω, 5% resistors
20kΩ, 5% resistor
PCLKI+,
PCLKI-, PD0+,
PD0-, PD1+,
PD1-, PD2+,
PD2-, PD3+,
PD3-, PCLK0+,
PCLK0-
The evaluation kit is designed to directly couple an
LVDS reference clock. If the reference clock does not
have LVDS-compatible levels:
12
SMB connectors (PC-mount)
SMA connectors (PC-mount)
1) Cut the PC board traces shorting capacitors C1
and C2.
2) Install 0.1µF capacitors.
RCLK+, RCLK-,
SD+, SD-
4
3) Install 4.99kΩ resistors for R1 and R2 and tie the
centerpoint of R1 and R2 (available at JU1) to
GND, +3.3V
2
1
1
1
1
1
Test points
V
CC
/ 2. Install a 0.1µF capacitor at C3 for add-
JU3
U1
2x3 pin header
tional noise filtering.
MAX3693ECJ (32 TQFP)
MAX3693 PC board
MAX3693 data sheet
Shunt for JU3
The PECL outputs have an attenuation (0.6) and imped-
ance matching network on the EV board that allow 50Ω
terminations to ground for oscilloscope interfacing. All
signal inputs and outputs use coupled 50Ω transmis-
sion lines. All input signal lines are of equal length to
minimize propagation-delay skew. Likewise, all output
signal lines are of equal length.
Co m p o n e n t S u p p lie rs
The MAX3693 EV kit allows use of multiple reference
clock frequencies with the appropriate setting on JU3.
See Table 1 for jumper settings.
SUPPLIER
AVX
PHONE
FAX
803-946-0690
847-639-6400
803-626-3123
847-639-1469
Coilcraft
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.