19-1212; Rev 0; 3/97
MAX3 6 8 0 Eva lu a t io n Kit
Evluates:MAX3680
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ Single +3.3V Supply
The MAX3680 evaluation kit (EV kit) simplifies evalua-
tion of the MAX3680 622Mbps, SDH/SONET 1:8 deseri-
alizer. The EV kit requires only a +3.3V supply, and
includes all the external components necessary to inter-
face with 3.3V PECL/TTL logic. The board can be con-
nected directly to the output of a clock-and-data-recov-
ery circuit (such as the MAX3675) and to the TTL input
of an overhead termination circuit. It can also be used
with a signal generator and an oscilloscope to evaluate
the MAX3680’s basic functionality.
♦ Inputs Terminated for Interfacing with 3.3V PECL
♦ Outputs Configured for 50Ω or High-Impedance
Interface
♦ Fully Assembled and Tested
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
BOARD TYPE
MAX3680EVKIT-SO
-40°C to +85°C
Surface Mount
____________________Co m p o n e n t Lis t
DESIGNATION QTY
DESCRIPTION
C1–C4
4
0.1µF ceramic capacitors
_______________De t a ile d De s c rip t io n
33µF, 10V tantalum capacitor
AVX TAJC336K010 or
Sprague 293D336X0010C2
The MAX3680 EV kit s imp lifie s e va lua tion of the
MAX3680 622Mbps, SDH/SONET 1:8 deserializer. The
EV kit op e ra te s from a s ing le + 3.3V s up p ly a nd
includes all the external components necessary to inter-
face with 3.3V PECL/TTL logic.
C5
1
2.2µF tantalum capacitor
AVX TAJA225K010 or
Sprague 293D225X0010A2
C6
1
Each PECL input (SCLK+, SCLK-, SD+, SD-) is termi-
nated on the EV board with the Thevenin equivalent of
C7–C12
J3–J16
6
100pF ceramic capacitors
14
SMA connectors (PC edge mount)
50Ω to (V - 2V). These inputs can be driven directly
CC
56nH inductor
Coilcraft 0805CS-560-XKBC
by any 3.3V PECL device's output, such as a clock-
and-data-recovery circuit (e.g., the MAX3675). The syn-
chronization input (SYNC) is a TTL input.
L1
1
4
R1, R3, R5, R7
82Ω, 5% resistors
The TTL outputs (PCLK, PD_) can interface to either
50Ω or high-impedance inputs. To interface to 50Ω
inputs, connect the inputs directly to the SMA connec-
tors labeled PCLK and PD0–PD7. This configuration
forms a 50-to-1 voltage divider that maintains a high-
impedance load to each TTL output while interfacing to
50Ω. To interface to high-impedance inputs, connect
the inputs to the 2-pin headers at R9–R17, which pro-
vide direct connections to the TTL outputs.
R2, R4, R6, R8
R9–R17
4
9
130Ω, 5% resistors
2.4kΩ, 5% resistors
+3.3V, GND
JR9–JR17
11
2-pin headers
U1
1
1
MAX3680EAI
None
MAX3680 data sheet
_____________La yo u t Co n s id e ra t io n s
______________Co m p o n e n t S u p p lie rs
To minimize propagation-delay skew, all PECL input
signal lines are 50Ω transmission lines of equal length.
To allow accurate characterization of the parallel-clock
to data-output delay, the output data lines (prior to the
series 2.4kΩ termination resistors) are matched and
kept as short as possible. Excluding the series termina-
tion resistor, each output data line measures approxi-
mately 3pF at the 2-pin header (JR9–JR17).
SUPPLIER
AVX
PHONE
FAX
(803) 946-0690
(847) 639-6400
(603) 224-1961
(803) 626-3123
(847) 639-1469
(603) 224-1430
Coilcraft
Sprague
Please indicate that you are using the MAX3680 when contact-
ing the above component suppliers.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.