DS3161/DS3162/DS3163/DS3164
Single/Dual/Triple/Quad
ATM/Packet PHYs for DS3/E3/STS-1
www.maxim-ic.com
FUNCTIONAL DIAGRAM
GENERAL DESCRIPTION
The DS3161, DS3162, DS3163, and DS3164
(DS316x)
integrate ATM
cell/HDLC
packet
processor(s) with DS3/E3 framer(s) to map/demap
ATM cells or packets into as many as four DS3/E3
digital lines with DS3-framed, E3-framed, or clear-
channel data streams on per-port basis.
POS-PHY
or
DS3/E3
FRAMER/
CELL/
PACKET
DS3/E3 LINE
INTERFACE
UTOPIA
FORMATTER
PROCESSOR
APPLICATIONS
Access Concentrators Multiservice Access
Platform (MSAP)
SONET/SDH ADM
SONET/SDH Muxes
PBXs
DS316x
Multiservice Protocol
Platform (MSPP)
FEATURES
Digital Cross Connect ATM and Frame Relay
Test Equipment
Equipment
ꢀ
Single (DS3161), Dual (DS3162), Triple
(DS3163), or Quad (DS3164) ATM/Packet PHYs
for DS3, E3, and Clear-Channel 52Mbps (CC52)
Routers and Switches PDH Multiplexer/
Demultiplexer
Integrated Access
ꢀ
Pin Compatible for Ease of Port Density
Device (IAD)
Migration in the Same PC Board Platform
ORDERING INFORMATION
ꢀ
ꢀ
Each Port Independently Configurable
PART
TEMP RANGE PIN-PACKAGE
Universal PHYs Map ATM Cells and/or HDLC
400 TE-PBGA (27mm x
Packets into DS3 or E3 Data Streams
DS3161
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
27mm, 1.27mm pitch)
ꢀ
UTOPIA L2/L3 or POS-PHY™ L2/L3 or SPI-3
Interface with 8-, 16-, or 32-Bit Bus Width
400 TE-PBGA (27mm x
DS3161N
DS3162
27mm, 1.27mm pitch)
ꢀ
ꢀ
ꢀ
66MHz UTOPIA L3 and POS-PHY L3 Clock
52MHz UTOPIA L2 and POS-PHY L2 Clock
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
400 TE-PBGA (27mm x
DS3162N
DS3163
Ports Independently Configurable for Cell or
27mm, 1.27mm pitch)
Packet Traffic in POS-PHY Bus Modes
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
ꢀ
Direct, PLCP, DSS, and Clear-Channel Cell
Mapping
400 TE-PBGA (27mm x
DS3163N
DS3164
27mm, 1.27mm pitch)
ꢀ
ꢀ
Direct and Clear-Channel Packet Mapping
400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer(s)
400 TE-PBGA (27mm x
DS3164N
27mm, 1.27mm pitch)
ꢀ
ꢀ
Ports Independently Configurable for DS3, E3
(Full or Subrate) or Arbitrary Framing Protocols
Up to 52Mbps
Programmable (Externally Controlled or
Internally Finite State Machine Controlled)
Subrate DS3/E3
Note: Add the “+” suffix for the lead-free package option.
POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1
REV: 113006