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CDP1852D3 PDF预览

CDP1852D3

更新时间： 2024-02-06 21:52:32
品牌 Logo 应用领域
英特矽尔 - INTERSIL 外围集成电路
页数 文件大小 规格书
7页 208K
描述
High-Reliability Byte-Wide Input/Output Port

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CDP1852D3 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：SIDE BRAZED, CERAMIC, DIP-24
针数：24Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.8外部数据总线宽度：8
JESD-30 代码：R-CDIP-T24JESD-609代码：e0
I/O 线路数量：8端口数量：1
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
最大供电电压：10.5 V最小供电电压：4 V
标称供电电压：10 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
uPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches：1

CDP1852D3 数据手册

 浏览型号CDP1852D3的Datasheet PDF文件第2页浏览型号CDP1852D3的Datasheet PDF文件第3页浏览型号CDP1852D3的Datasheet PDF文件第4页浏览型号CDP1852D3的Datasheet PDF文件第5页浏览型号CDP1852D3的Datasheet PDF文件第6页浏览型号CDP1852D3的Datasheet PDF文件第7页 
TM  
CDP1852/3,  
CDP1852C/3  
March 1997  
High-Reliability Byte-Wide Input/Output Port  
Features  
Description  
• Static Silicon-Gate CMOS Circuitry  
• Parallel 8-Bit Data Register and Buffer  
• Handshaking Via Service Request Flip-Flop  
• Low Quiescent and Operating Power  
The CDP1852/3 and CDP1852C/3 are parallel, 8-bit, mode-  
programmable input/output ports. They are compatible and  
will interface directly with CDP1800-Series microprocessors.  
They are also useful as 8-bit address latches when used  
with the CDP1800 multiplexed address bus and as I/O ports  
in general-purpose applications.  
• Interfaces Directly with CDP1800-Series Microproces-  
sors  
The mode control is used to program the device as an input  
port (mode = 0) or as an output port (mode = 1). The SR/SR  
output can be used as a signal to indicate when data is  
ready to be transferred. In the input mode, a peripheral  
device can strobe data into the CDP1852/3, and micropro-  
cessor can read that data by device selection. In the output  
mode, a microprocessor strobes data into the CDP1852/3,  
and handshaking is established with a peripheral device  
when the CDP1852/3 is deselected.  
• Single Voltage Supply  
• Full Military Temperature Range  
(-55oC to +125oC)  
Ordering Information  
In the input mode, data at the data-in terminals (DI0-DI7) is  
strobed into the port’s 8-bit register by a high (1) level on the  
clock line. The negative high-to-low transition of the clock  
latches the data in the register and sets the service request  
output low (SR/SR = 0). When CS1/CS1 and CS2 are high  
(CS1/CS1 and CS2 = 1), the three-state output drivers are  
enabled and data in the 8-bit register appear at the data-out  
terminals (DO0-DO7). When either CS1/CS1 or CS2 goes low  
(CS1/CS1 or CS2 = 0), the data-out terminals are tristated  
and the service request output returns high (SR/SR =1).  
PACK-  
AGE  
TEMP.  
RANGE  
PKG.  
NO  
5V  
10V  
o
o
SBDIP  
-55 C to +125 C CDP1852CD3 CDP1852D3 D24.6  
Pinout  
CDP1852/3, CDP1852C/3 (SBDIP)  
TOP VIEW  
In the output mode, the output drivers are enabled at all  
times. Data at the data-in terminals (DI0-DI7) is strobed into  
the 8-bit register when CS1/CS1 is low (CS1/CS1 = 0) and  
CS2 and the clock are high (1), and are present at the data-  
out terminals (DO0-DO7). The negative high-to-low transi-  
tion of the clock latches the data in the register. The SR/SR  
output goes high (SR/SR = 1) when the device is deselected  
(CS1/CS1 = 1 or CS2 = 0) and returns low (SR/SR = 0) on the  
following trailing edge of the clock.  
CSI/CSI  
MODE  
DI0  
1
2
3
4
5
6
7
8
9
24  
VDD  
23 SR/SR  
22 DI7  
21 DO7  
20 DI6  
DO0  
DI1  
DO1  
DI2  
19 DO6  
18 DI5  
DO2  
DI3  
17 DO5  
16 DI4  
A CLEAR control is provided for resetting the port’s register  
(DO0-DO7  
= 0) and service request flip-flop (input  
DO3 10  
CLOCK 11  
VSS 12  
15 DO4  
14 CLEAR  
13 CS2  
mode: SR/SR = 1 and output mode: SR/SR = 0).  
The CDP1852/3 is functionally identical to the CDP1852C/3.  
The CDP1852/3 has a recommended operating voltage  
range of 4V to 10.5V, and the CDP1852C/3 has a recom-  
mended operating voltage range of 4V to 6.5V.  
The CDP1852/3 and CDP1852C/3 are supplied in 24-lead,  
dual-in-line side-brazed ceramic packages (D suffix).  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
File Number 1694.2  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
1
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