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CDP1821CD3 PDF预览

CDP1821CD3

更新时间: 2024-02-13 09:45:49
品牌 Logo 应用领域
英特矽尔 - INTERSIL 内存集成电路静态存储器
页数 文件大小 规格书
7页 36K
描述
High-Reliability CMOS 1024-Word x 1-Bit Static RAM

CDP1821CD3 技术参数

生命周期:ActiveReach Compliance Code:unknown
风险等级:5.79Is Samacsys:N
最长访问时间:255 nsJESD-30 代码:R-CDIP-T16
内存密度:1024 bit内存集成电路类型:STANDARD SRAM
内存宽度:1功能数量:1
端子数量:16字数:1024 words
字数代码:1000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:1KX1封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL认证状态:COMMERCIAL
最大供电电压 (Vsup):6.5 V最小供电电压 (Vsup):4 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子位置:DUAL
Base Number Matches:1

CDP1821CD3 数据手册

 浏览型号CDP1821CD3的Datasheet PDF文件第2页浏览型号CDP1821CD3的Datasheet PDF文件第3页浏览型号CDP1821CD3的Datasheet PDF文件第4页浏览型号CDP1821CD3的Datasheet PDF文件第5页浏览型号CDP1821CD3的Datasheet PDF文件第6页浏览型号CDP1821CD3的Datasheet PDF文件第7页 
CDP1821C/3  
High-Reliability CMOS  
1024-Word x 1-Bit Static RAM  
March 1997  
Features  
Description  
• Static CMOS Silicon-On-Sapphire Circuitry CD4000-  
Series Compatible  
The CDP1821C/3 is a 1024-word x 1-bit CMOS silicon-on-sap-  
phire (SOS), fully static, random-access memory designed for  
use in CDP1800 microprocessor systems. This device has a  
recommended operating voltage range of 4V to 6.5V.  
• Compatible with CDP1800-Series Microprocessors at  
Maximum Speed  
The output state of the CDP1821C/3 is a function of the  
input address and chip-select states only. Valid data will  
appear at the output in one access time following the latest  
address change to a selected chip. After valid data appears,  
the address may be changed immediately. It is not neces-  
sary to clock the chip-select input or any other input terminal  
for fully static operation; therefore the chip-select input may  
be used as an additional address input. When the device is  
in an unselected state (CS = 1), the internal write circuitry  
and output sense amplifier are disabled. This feature allows  
the three-state data outputs from many arrays to be OR-tied  
to a common bus for easy memory expansion.  
• Fast Access Time. . . . . . . . . . . 100ns Typ. at V  
• Single Voltage Supply  
= 5V  
DD  
• No Precharge or External Clocks Required  
• Low Quiescent and Operating Power  
• Separate Data Inputs and Outputs  
• High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of V  
DD  
• Memory Retention for Standby Battery Voltage Down  
o
to 2V at +25 C  
• Latch-Up-Free Transient-Radiation Tolerance  
Ordering Information  
PART  
PACKAGE  
TEMP. RANGE  
NUMBER  
PKG. NO.  
o
o
SBDIP  
-55 C to +125 C CDP1821CD3 D16.3  
Pinout  
CDP1821C/3  
(SBDIP)  
TOP VIEW  
CS  
A0  
A1  
A2  
A3  
A4  
DO  
1
2
3
4
5
6
7
8
16 V  
DD  
15 DI  
14 RD/WR  
13 A9  
12 A8  
11 A7  
10 A6  
9
A5  
V
SS  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 2983.1  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19996-5  

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