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278106-002

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
英特尔 - INTEL		PC
页数	文件大小	规格书
164页	1344K
描述
PCI-to-PCI Bridge

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278106-002 数据手册

21150 PCI-to-PCI Bridge

Preliminary Datasheet

Product Features

■ Complies fully with the PCI Local Bus

■ Provides a 4-pin general-purpose I/O

interface, accessible through device-

specific configuration space

Specification, Revision 2.1

■ Complies fully with the Advanced

Configuration Power Interface (ACPI)

Specification

■ Provides enhanced address decoding:

—A 32-bit I/O address range

■ Complies fully with the PCI Power

— A 32-bit memory-mapped I/O address

range

Management Specification, Revision 1.0¹

■ Complies fully with Revision 1.0 of the

PCI-to-PCI Bridge Architecture

Specification

— A 64-bit prefetchable memory address

range

— ISA-aware mode for legacy support in

the first 64KB of I/O address range

■ Implements delayed transactions for all PCI

configuration, I/O, and memory read

commands—up to three transactions

simultaneously in each direction

— VGA addressing and VGA palette

snooping support

■ Allows 88 bytes of buffering (data and

address) for posted memory write

commands in each direction—up to five

posted write transactions simultaneously in

each direction

■

Includes live insertion support

■ Supports PCI transaction forwarding for the

following commands:

— All I/O and memory commands

■ Allows 72 bytes of read data buffering in

— Type 1 to Type 1 configuration

commands

each direction

■ Provides concurrent primary and secondary

— Type 1 to Type 0 configuration

commands (downstream only)

bus operation, to isolate traffic

■ Provides 10 secondary clock outputs with

— All Type 1 to special cycle

configuration commands

the following features:

—Low skew permits direct drive of option

slots

■ Includes downstream lock support

■ Supports both 5-V and 3.3-V signaling

—Individual clock disables, capable of

automatic configuration during reset

environments

■ Available in both 33 MHz and 66 MHz

■ Provides arbitration support for nine

versions

secondary bus devices:

■ Provides an IEEE standard 1149.1 JTAG

— A programmable 2-level arbiter

interface.

— Hardware disable control, to permit use

of an external arbiter

^1.For 21150-AB and later revisions only. The 21150-AA does not implement this feature.

Notice: This document contains preliminary information on new products in production. The

specifications are subject to change without notice. Verify with your local Intel sales office that

you have the latest datasheet before finalizing a design.

Order Number: 278106-002

July 1998

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