PCI Bridges - Products: 21154 Transparent PCI-to-PCI Bridge
21154 Transparent PCI-to-PCI Bridge
The 21154AC and 21154BC transparent PCI-to-PCI Bridges are Not Recommended for
new designs. For 33 MHz applications use the FW21154AE. For 66 MHz
applications use the FW21154BE.
The 21154 PCI-to-PCI bridge is designed for compliance with PCI Local Bus Specification,
Revision 2.2. The 21154 has a 64-bit primary bus interface and a 64-bit secondary interface.
Technical Quick List
Application Notes
Datasheets
Linecard
This chip, which is used on motherboards and add-in cards, allows a system designer to
increase data throughput in a variety of data intensive server, workstation and high-end PC
applications including networking and data storage. The 21154 is available in a 64-bit version
and is PCI Local Bus Specification, Revision 2.2 compliant.
Manuals
The 21154 provides full support for delayed transactions, which enables the buffering of
memory read, I/O, and configuration transactions. The 21154 has separate posted write, read
data, and delayed transaction queues with significant buffering capability. In addition, the
21154 supports buffering of simultaneous, multiple, posted write and delayed transactions in
both directions.
Guides
Software
IBIS
BSDL
Specification Updates
Schematics
Among the features of the 21154 are: a programmable 2-level secondary bus arbiter, an IEEE
standard 1149.1 JTAG interface, live insertion support, a 4-pin general-purpose I/O interface,
individual secondary clock disables, and enhanced address decoding. The 21154 has enough
clock and arbitration pins to support nine PCI bus master devices directly on its secondary
interface.
Frequently Asked
Questions
The 21154 allows the two PCI buses to operate concurrently. This means that a master and a
target on the same PCI bus can communicate while the other PCI bus is busy. This traffic
isolation may increase system performance in applications such as multimedia.
Where to Buy
Features
● Designed for compliance with PCI Local Bus Specification, Revision 2.2
● Supports 64-bit extension signals on the primary and secondary interfaces
● Implements delayed transactions for all PCI configuration, I/O, and memory read
commands – up to three transactions simultaneously in each direction
● Allows 152 bytes of buffering (data and address) for upstream posted memory write
commands and 88 bytes of buffering for downstream posted memory write commands
● Allows 152 bytes of read data buffering upstream and 72 bytes of read data buffering
downstream
● Provides concurrent primary and secondary bus operation to isolate traffic
● Provides ten secondary clock outputs:
❍ Low skew, permitting direct drive of option slots
❍ Individual clock disables, capable of automatic configuration during reset
● Provides arbitration support for nine secondary bus devices:
❍ A programmable 2-level arbiter
❍ Hardware disable control, permitting use of an external arbiter
● Provides a 4-pin general-purpose I/O interface, accessible through device-specific
configuration space
● Provides enhanced address decoding:
❍ A 32-bit I/O address range