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MK3720BLF PDF预览

MK3720BLF

更新时间: 2024-02-14 13:37:10
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
6页 100K
描述
Clock Generator, 54MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

MK3720BLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.22
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm湿度敏感等级:1
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:54 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260主时钟/晶体标称频率:13.5 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压:3.45 V最小供电电压:3.15 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

MK3720BLF 数据手册

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MK3720  
27 MHZ AND 54 MHZ 3.3 VOLT VCXO  
The frequency of the on-chip VCXO is adjusted by an  
external control voltage input into pin VIN. Because  
Description  
VIN is a high impedance input, it can be driven directly  
from an PWM RC integrator circuit.  
The MK3720D and MK3720B are drop-in replacements  
for the MK3720S and MK3720A devices. Compared to  
these earlier devices the MK3720D and MK3720B offer  
a wider operating frequency range and improved power  
supply noise rejection.  
Features  
MK3720D and MK3720B are drop-in upgrades to the  
earlier MK3720S and MK3720A devices  
The MK3720 is a low-cost, low-jitter, high-performance  
3.3 Volt VCXO designed to replace expensive 13.5, 27,  
or 54 MHz VCXOs. The patented on-chip Voltage  
Controlled Crystal Oscillator accepts a 0 to 3.3 V input  
voltage to cause the output clocks to vary by 100 ppm.  
Using ICS’ patented VCXO and analog/digital  
Phase-Locked Loop (PLL) techniques, the device uses  
an inexpensive external pullable crystal input to  
produce output clocks of 13.5 MHz, 27 MHz, and 54  
MHz.  
Packaged in 8-pin SOIC  
Available in Pb (lead) free package (MK3720D only)  
Operating voltage of 3.3 V ( 5%)  
Output clocks of 54, 27, and 13.5 MHz  
Uses an inexpensive 13.500 MHz external crystal  
On-chip VCXO (patented) with pull range of 200ppm  
(minimum)  
VCXO tuning voltage of 0 to 3.3V  
The MK3720D exhibits a moderate VCXO gain of 120  
ppm/V typical, when used with a high-quality external  
pullable quartz crystal. The MK3720B offers a higher  
VCXO gain of 150 ppm/V, similar to the earlier  
MK3720A. The higher intrinsic VCXO gain of the  
MK3720B may help compensate for the reduced  
pullability of a low quality crystal used in some  
applications. However, higher VCXO gain may also  
increase clock output phase noise.  
12 mA output drive capability at TTL levels  
Advanced, low-power, sub-micron CMOS process  
MK3720D is Recommended for New Designs  
Block Diagram  
VDD  
VIN  
54 M Hz  
PLL/Clock  
Synthesis  
Circuitry  
X1  
13.5 M Hz  
Pullable  
Voltage  
Controlled  
Crystal  
Oscillator  
27 M Hz  
Crystal  
X2  
13.5 M Hz  
GND  
MDS 3720 H  
1
Revision 052504  
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com  

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