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IDT77V500S25PFG PDF预览

IDT77V500S25PFG

更新时间: 2024-02-05 01:14:07
品牌 Logo 应用领域
艾迪悌 - IDT 开关控制器异步传输模式ATM
页数 文件大小 规格书
17页 450K
描述
ATM Switching Circuit, 1-Func, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

IDT77V500S25PFG 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP, QFP100,.63SQ,20
针数:100Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.87
Is Samacsys:N应用程序:ATM
JESD-30 代码:S-PQFP-G100JESD-609代码:e0
长度:14 mm湿度敏感等级:3
功能数量:1端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
子类别:ATM/SONET/SDH ICs最大压摆率:0.2 mA
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH SWITCHING CIRCUIT温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

IDT77V500S25PFG 数据手册

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TM  
IDT77V500  
SwitchStar ATM Cell Based  
1.2Gbps non-blocking  
Integrated Switch Controller  
One IDT77V500 can manage up to eight IDT77V400's  
Features  
without derating for larger switch configurations  
Industrial temperature range (-40° C to +85° C) is available  
Single +3.3V ± 300mV power supply  
Single chip controller for IDT77V400 Switching Memory  
One IDT77V500 and one IDT77V400 form the core required  
for a 1.2Gbps 8 x 8 port non-blocking switch  
Available in a 100-pin Thin Plastic Quad Flat Pack (TQFP)  
Supports up to 8192 Virtual Connections (VCs)  
and 144-ball BGA  
Per VC queuing for fairness, with four priorities per VC  
available for each output port of the switch  
Description  
Capable of supporting CBR, VBR, UBR, and ABR (EFCI)  
service classes  
The IDT77V500 ATM Cell Based Switch Controller, when paired with  
the IDT77V400 Switching Memory, forms the core control logic and  
switch fabric for a 1.2Gbps non-blocking ATM switch. The IDT77V500  
manages all of the switch traffic moving through the IDT77V400,  
commanding the storage of incoming ATM cells and interpreting and  
modifying the cell header information as necessary for data flow through  
the switch. It then uses the header information, including priority indica-  
tors, to queue and direct the individual cells for transmission out the  
appropriate output port of the IDT77V400.  
Low power dissipation  
430mW (typ.)  
Optional header modification operation  
Multicasting and Broadcasting capability  
Provides congestion management support through EFCI,  
CLP, and EPD functionality  
System clock cycle times as fast as 25ns (40MHz)  
Option available for resolving contention issues between  
multiple IDT77V500 configurations  
Typical 8 x 8 Switch Configuration using the IDT77V500 Switch Controller  
External Interface  
for Global Setup  
and Control  
Data  
8-bit Processor/  
Call Setup  
Manager  
/
IDT77V500  
Control  
Switch  
Controller  
or IDT77V550  
Data  
Control  
Port 0  
Port 0  
155Mbps  
PHY  
155Mbps  
PHY  
IDT77V400  
Switching  
Memory  
Port 7  
Port 7  
155Mbps  
PHY  
155Mbps  
PHY  
,
3607 drw 01  
SwitchStar and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
2001 Integrated Device Technology, Inc.  
1 of 17  
April 11, 2001  
DSC 3607/5  

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