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IDT77V1264L200PGI PDF预览

IDT77V1264L200PGI

更新时间: 2024-01-03 14:18:18
品牌 Logo 应用领域
艾迪悌 - IDT ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
49页 391K
描述
Quad Port PHY (Physical Layer) for 25.6, 51.2, and 204.8 Mbps ATM Networks and Backplane Applications

IDT77V1264L200PGI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:QFP,
针数:144Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.24
Is Samacsys:N应用程序:ATM
JESD-30 代码:S-PQFP-G144长度:28 mm
功能数量:1端子数量:144
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:4.07 mm标称供电电压:3.3 V
表面贴装:YES技术:CMOS
电信集成电路类型:ATM/SONET/SDH NETWORK INTERFACE温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:28 mmBase Number Matches:1

IDT77V1264L200PGI 数据手册

 浏览型号IDT77V1264L200PGI的Datasheet PDF文件第2页浏览型号IDT77V1264L200PGI的Datasheet PDF文件第3页浏览型号IDT77V1264L200PGI的Datasheet PDF文件第4页浏览型号IDT77V1264L200PGI的Datasheet PDF文件第5页浏览型号IDT77V1264L200PGI的Datasheet PDF文件第6页浏览型号IDT77V1264L200PGI的Datasheet PDF文件第7页 
Quad Port PHY (Physical Layer)  
for 25.6, 51.2, and 204.8 Mbps  
ATM Networks and Backplane  
Applications  
IDT77V1264L200  
Description  
Features List  
!
Performs the PHY-Transmission Convergence (TC) and  
The IDT77V1264L200 is a member of IDT's family of products  
supporting Asynchronous Transfer Mode (ATM) data communications  
and networking. The IDT77V1264L200 implements the physical layer for  
25.6 Mbps ATM, connecting four serial copper links (UTP Category 3  
and 5) to one ATM layer device such as a SAR or a switch ASIC. The  
IDT77V1264L200 also operates at 51.2 Mbps and 204.8 Mbps, and is  
well suited to backplane driving applications.  
Physical Media Dependent (PMD) Sublayer functions for  
four 204.8 Mbps ATM channels  
!
Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5  
specifications for 25.6 Mbps physical interface  
!
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Operates at 25.6, 51.2, 102.4, 204.8 Mbps data rates  
Individual Selection of Port Data Rates  
Backwards Compatible with 77V1254L25  
UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface  
3-Cell Transmit and Receive FIFOs  
The 77V1264L200-ATM layer interface is selectable as either: 16-bit  
UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or quadruple 4-bit  
DPI (Data Path Interface).  
The IDT77V1264L200 is fabricated using IDT's state-of-the-art  
CMOS technology, providing the highest levels of integration, perfor-  
mance and reliability, with the low-power consumption characteristics of  
CMOS.  
LED Interface for status signalling  
Supports UTP Category 3 and 5 physical media  
Low-Power CMOS  
3.3V supply with 5V tolerant inputs  
144-pin PQFP Package (28 x 28 mm)  
Industrial Temperature Ranges  
Block Diagram  
TXREF  
TXCLK  
TXDATA[15:0]  
TXPARITY  
TXSOC  
+
-
TX 0  
RX 0  
Driver  
5B/4B  
Encoding/  
Decoding  
TX/RX ATM  
Cell FIFO  
Scrambler/  
Descrambler  
P/S and S/P  
NRZI  
+
-
TXEN  
TXCLAV  
Clock Recovery  
TXADDR[4:0]  
MODE[1:0]  
PHY-ATM  
Interface  
(UTOPIA or DPI)  
+
-
RXADDR[4:0]  
RXCLK  
RXDATA[15:0]  
RXPARITY  
RXSOC  
Tx 1  
Rx 1  
Driver  
5B/4B  
Encoding/  
Decoding  
TX/RX ATM  
Cell FIFO  
Scrambler/  
Descrambler  
P/S and S/P  
NRZI  
+
-
Clock Recovery  
RXEN  
RXCLAV  
+
-
INT  
RST  
TX 2  
RX 2  
Driver  
5B/4B  
Encoding/  
Decoding  
TX/RX ATM  
Cell FIFO  
Scrambler/  
Descrambler  
P/S and S/P  
NRZI  
+
-
Clock Recovery  
Microprocessor  
Interface  
RD  
WR  
CS  
AD[7:0]  
+
-
ALE  
TX 3  
RX 3  
Driver  
5B/4B  
Encoding/  
Decoding  
TX/RX ATM  
Cell FIFO  
Scrambler/  
Descrambler  
P/S and S/P  
NRZI  
+
-
Clock Recovery  
OSC  
4
4
RXREF  
RXLED[3:0] TXLED[3:0]  
3505 drw 01  
.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.  
1 of 49  
December 2004  
DSC 6029/1  
2004 Integrated Device Technology, Inc. All rights reserved. Product specification subject to change without notice.  

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