IDT77V1254L25
Quad Port PHY (Physical Layer)
for 25.6 and 51.2
ATM Networks
Features List
Description
Performs the PHY-Transmission Convergence (TC) and
The IDT77V1254L25 is a member of IDT's family of products
supporting Asynchronous Transfer Mode (ATM) data communications
and networking. The IDT77V1254L25 implements the physical layer for
25.6 Mbps ATM, connecting four serial copper links (UTP Category 3
and 5) to one ATM layer device such as a SAR or a switch ASIC. The
IDT77V1254L25 also operates at 51.2 Mbps, and is well suited to back-
plane driving applications.
Physical Media Dependent (PMD) Sublayer functions for
four 25.6 Mbps ATM channels
Compliant to ATM Forum (af-phy-040.000) and ITU-T I.432.5
specifications for 25.6 Mbps physical interface
Also operates at 51.2 Mbps data rate
UTOPIA Level 1, UTOPIA Level 2, or DPI-4 Interface
3-Cell Transmit & Receive FIFOs
The 77V1254L25-to-ATM layer interface is selectable as one of three
options: 16-bit UTOPIA Level 2, 8-bit UTOPIA Level 1 Multi-PHY, or
quadruple 4-bit DPI (Data Path Interface).
The IDT77V1254L25 is fabricated using IDT's state-of-the-art CMOS
technology, providing the highest levels of integration, performance and
reliability, with the low-power consumption characteristics of CMOS.
LED Interface for status signalling
Supports UTP Category 3 and 5 physical media
Interfaces to standard magnetics
Low-Power CMOS
3.3V supply with 5V tolerant inputs
144-pin PQFP Package (28 x 28 mm)
Commercial and Industrial Temperature Ranges
Block Diagram
TXREF
T X C LK
T X D A T A [15:0]
T X P A R IT Y
+
-
T X
0
0
D river
5B /4B
E ncoding/
D ecoding
T X /R X A T M
C ellF IF O
S cram bler/
D escram bler
P /S and S /P
N R Z I
T X S O
C
+
-
TXEN
T X C LA V
C lock R ecovery
R X
T X A D D R [4 :0 ]
P H Y -A T M
Interface
M
O D E [1:0]
(U T O P IA or D P I)
+
-
R X A D D R [4:0]
R X C LK
T x
1
D river
5B /4B
E ncoding/
D ecoding
T X /R X A T M
C ellF IF O
S cram bler/
D escram bler
P /S and S /P
N R Z I
R X D A T A [15:0]
R X P A R IT Y
+
-
C lock R ecovery
R x
1
R X S O
C
RXEN
R X C LA V
+
-
INT
RST
T X
2
2
D river
5B /4B
E ncoding/
D ecoding
T X /R X A T M
C ellF IF O
S cram bler/
D escram bler
P /S and S /P
N R Z I
+
-
C lock R ecovery
R X
M
icroprocessor
Interface
RD
WR
CS
A D [7:0]
+
-
A LE
T X
3
3
D river
5B /4B
E ncoding/
D ecoding
T X /R X A T M
C ellF IF O
S cram bler/
D escram bler
P /S and S /P
N R Z I
+
-
C lock R ecovery
R X
O
S C
4
4
RXREF
35 0 5 drw 0 1
R X LE D [3:0]
T X LE D [3:0]
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 47
September 21, 2001
DSC 6003
2001 Integrated Device Technology, Inc.