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IDT72V821L15PFI PDF预览

IDT72V821L15PFI

更新时间: 2024-01-16 22:21:58
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
16页 147K
描述
FIFO, 1KX9, 10ns, Synchronous, CMOS, PQFP64, PLASTIC, TQFP-64

IDT72V821L15PFI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:PLASTIC, TQFP-64针数:64
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.32
最长访问时间:10 ns最大时钟频率 (fCLK):66.7 MHz
周期时间:15 nsJESD-30 代码:S-PQFP-G64
JESD-609代码:e0长度:14 mm
内存密度:9216 bit内存集成电路类型:OTHER FIFO
内存宽度:9湿度敏感等级:3
功能数量:1端子数量:64
字数:1024 words字数代码:1000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:1KX9
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP64,.66SQ,32
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.01 A
子类别:FIFOs最大压摆率:0.04 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

IDT72V821L15PFI 数据手册

 浏览型号IDT72V821L15PFI的Datasheet PDF文件第2页浏览型号IDT72V821L15PFI的Datasheet PDF文件第3页浏览型号IDT72V821L15PFI的Datasheet PDF文件第4页浏览型号IDT72V821L15PFI的Datasheet PDF文件第5页浏览型号IDT72V821L15PFI的Datasheet PDF文件第6页浏览型号IDT72V821L15PFI的Datasheet PDF文件第7页 
IDT72V801  
IDT72V811  
IDT72V821  
IDT72V831  
IDT72V841  
IDT72V851  
3.3 VOLT DUAL CMOS SyncFIFO™  
DUAL 256 X 9, DUAL 512 X 9,  
DUAL 1,024 X 9, DUAL 2,048 X 9,  
DUAL 4,096 X 9 , DUAL 8,192 X 9  
EachofthetwoFIFOs(designatedFIFOAandFIFOB)containedinthe  
IDT72V801/72V811/72V821/72V831/72V841/72V851hasa9-bitinputdata  
port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8,  
QB0 - QB8).Eachinputportis controlledbya free-runningclock(WCLKA,  
WCLKB), and two Write Enable pins (WENA1, WENA2, WENB1, WENB2).  
DataiswrittenintoeachofthetwoarraysoneveryrisingclockedgeoftheWrite  
Clock (WCLKA, WCLKB) when the appropriate Write Enable pins are  
asserted.  
TheoutputportofeachFIFObankiscontrolledbyitsassociated clockpin  
(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,  
RENB2).TheReadClockcanbetiedtotheWriteClockforsingleclockoperation  
orthetwoclockscanrunasynchronousofoneanotherfordualclockoperation.  
AnOutputEnablepin(OEA,OEB)is providedonthereadportofeachFIFO  
forthree-stateoutputcontrol.  
ꢀEATURES:  
The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs  
The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs  
The IDT72V821 is equivalent to two IDT72V221 1,024 x 9 FIFOs  
The IDT72V831 is equivalent to two IDT72V231 2,048 x 9 FIFOs  
The IDT72V841 is equivalent to two IDT72V241 4,096 x 9 FIFOs  
The IDT72V851 is equivalent to two IDT72V251 8,192 x 9 FIFOs  
Offers optimal combination of large capacity, high speed,  
design flexibility and small footprint  
Ideal for prioritization, bidirectional, and width expansion  
applications  
10 ns read/write cycle time  
5V input tolerant  
Separate control lines and data lines for each FIFO  
Separate Empty, Full, programmable Almost-Empty and  
Almost-Full flags for each FIFO  
Enable puts output data lines in high-impedance state  
Space-saving 64-pin plastic Thin Quad Flat Pack (TQFP/  
STQFP)  
EachofthetwoFIFOshastwofixedflags,Empty(EFA,EFB)andFull(FFA,  
FFB). Twoprogrammableflags,Almost-Empty(PAEA,PAEB)andAlmost-Full  
(PAFA,PAFB),areprovidedforeachFIFObanktoimprovememoryutilization.  
Ifnotprogrammed,theprogrammableflagsdefaulttoEmpty+7forPAEAand  
PAEB, and Full-7 for PAFA and PAFB.  
TheIDT72V801/72V811/72V821/72V831/72V841/72V851architecture  
lendsitselftomanyflexibleconfigurationssuchas:  
Industrial temperature range (–40°C to +85°C) is available  
• 2-levelprioritydatabuffering  
Bidirectionaloperation  
DESCRIPTION:  
TheIDT72V801/72V811/72V821/72V831/72V841/72V851/72V851are  
dualsynchronous(clocked)FIFOs. Thedeviceisfunctionallyequivalentto  
twoIDT72V201/72V211/72V221/72V231/72V241/72V251FIFOsinasingle  
packagewithallassociatedcontrol,data,andflaglinesassignedtoseparate  
pins.  
Widthexpansion  
Depthexpansion  
ThisFIFOisfabricatedusingIDT'shigh-performancesubmicronCMOS  
technology.  
ꢀUNCTIONAL BLOCK DIAGRAM  
EFA  
PAEA  
PAFA  
FFA  
WCLKB  
WCLKA  
WENA1  
WENA2  
WENB1  
DA0 - DA8  
DB0 - DB8  
LDA  
LDB  
WENB2  
INPUT REGISTER  
OFFSET REGISTER  
INPUT REGISTER  
OFFSET REGISTER  
EFB  
FLAG  
LOGIC  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
WRITE CONTROL  
LOGIC  
PAEB  
PAFB  
FFB  
RAM ARRAY  
256 x 9, 512 x 9,  
1,024 x 9, 2,048 x 9,  
4,096 x 9, 8,192 x 9  
RAM ARRAY  
256 x 9, 512 x 9,  
1,024 x 9, 2,048 x 9,  
4,096 x 9, 8,192 x 9  
WRITE POINTER  
READ POINTER  
WRITE POINTER  
READ POINTER  
READ CONTROL  
LOGIC  
READ CONTROL  
LOGIC  
OUTPUT REGISTER  
OUTPUT REGISTER  
RESET LOGIC  
RESET LOGIC  
4093 drw 01  
RCLKB  
RENB1  
RENB2  
RSA  
OEA  
RSB  
RCLKA  
OEB  
QB0 - QB8  
QA0 - QA8  
RENA1  
RENA2  
The IDT logo is a registered trademark and the SyncFIFO is a trademark of Integrated Device Technology, Inc.  
APRIL 2001  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
2001 Integrated Device Technology, Inc.  
DSC-4093/1  

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