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IDT71V67703S75BG PDF预览

IDT71V67703S75BG

更新时间: 2024-01-16 02:11:50
品牌 Logo 应用领域
艾迪悌 - IDT 计数器存储内存集成电路静态存储器时钟
页数 文件大小 规格书
23页 976K
描述
256K X 36, 512K X 18 3.3V Synchronous SRAMs 3.3V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect

IDT71V67703S75BG 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:14 X 20 MM, 1.40 MM, PLASTIC, TQFP-100
针数:100Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.17最长访问时间:7.5 ns
其他特性:FLOW-THROUGH ARCHITECTURE最大时钟频率 (fCLK):117 MHz
I/O 类型:COMMONJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:9437184 bit内存集成电路类型:CACHE SRAM
内存宽度:36湿度敏感等级:3
功能数量:1端子数量:100
字数:262144 words字数代码:256000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.07 A
最小待机电流:3.14 V子类别:SRAMs
最大压摆率:0.285 mA最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:14 mmBase Number Matches:1

IDT71V67703S75BG 数据手册

 浏览型号IDT71V67703S75BG的Datasheet PDF文件第2页浏览型号IDT71V67703S75BG的Datasheet PDF文件第3页浏览型号IDT71V67703S75BG的Datasheet PDF文件第4页浏览型号IDT71V67703S75BG的Datasheet PDF文件第5页浏览型号IDT71V67703S75BG的Datasheet PDF文件第6页浏览型号IDT71V67703S75BG的Datasheet PDF文件第7页 
256K X 36, 512K X 18  
3.3VSynchronousSRAMs  
IDT71V67703  
IDT71V67903  
3.3V I/O, Burst Counter  
Flow-ThroughOutputs,SingleCycleDeselect  
Features  
data, address and control registers. There are no registers in the data  
outputpath(flow-througharchitecture). InternallogicallowstheSRAMto  
generateaself-timedwritebaseduponadecisionwhichcanbeleftuntil  
theendofthewritecycle.  
256K x 36, 512K x 18 memory configurations  
Supports fast access times:  
– 7.5ns up to 117MHz clock frequency  
– 8.0ns up to 100MHz clock frequency  
– 8.5ns up to 87MHz clock frequency  
Theburstmodefeatureoffersthehighestlevelofperformancetothe  
systemdesigner,astheIDT71V67703/7903canprovidefourcyclesof  
dataforasingleaddresspresentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
accesssequence.Thefirstcycleofoutputdatawillflow-throughfromthe  
arrayafteraclock-to-dataaccesstimedelayfromtherisingclockedgeof  
the same cycle. If burst mode operation is selected (ADV=LOW), the  
subsequentthreecyclesofoutputdatawillbeavailabletotheuseronthe  
next three rising clock edges. The order of these three addresses are  
definedbytheinternalburstcounterandtheLBO inputpin.  
LBO input selects interleaved or linear burst mode  
Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite  
enable (BWE), and byte writes (BWx)  
3.3V core power supply  
Power down controlled by ZZ input  
3.3V I/O supply (VDDQ)  
Packaged in a JEDEC Standard 100-pin thin plastic quad  
flatpack(TQFP),119ballgridarray(BGA)and165finepitchball  
grid array (fBGA).  
TheIDT71V67703/7903SRAMsutilizeIDT’slatesthigh-performance  
CMOSprocessandarepackagedinaJEDECstandard14mmx20mm  
100-pin thinplasticquadflatpack(TQFP)aswellasa119ballgridarray  
(BGA) and a 165 fine pitch ball grid array (fBGA).  
Description  
The IDT71V67703/7903 are high-speed SRAMs organized as  
256K x 36/512K x 18. The IDT71V67703/7903 SRAMs contain write,  
PinDescriptionSummary  
A0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
Chip Enable  
CE  
CS0, CS1  
OE  
Chip Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
Individual Byte Write Selects  
GW  
BWE  
(1)  
BW1, BW2, BW3, BW4  
CLK  
Clock  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
N/A  
Synchronous  
Synchronous  
Synchronous  
DC  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
Data Input / Output  
Core Power, I/O Power  
Ground  
Supply  
Supply  
VSS  
N/A  
5309 tbl 01  
NOTE:  
1. BW3 and BW4 are not applicable for the IDT71V67903.  
DECEMBER 2003  
1
©2002IntegratedDeviceTechnology,Inc.  
DSC-5309/05  

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