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ICS9DB803DFT PDF预览

ICS9DB803DFT

更新时间: 2024-02-10 04:15:50
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
20页 251K
描述
PLL Based Clock Driver, 9DB Series, 8 True Output(s), 0 Inverted Output(s), PDSO48, MO-118, SSOP-48

ICS9DB803DFT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP48,.4针数:48
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.24系列:9DB
输入调节:DIFFERENTIALJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:15.875 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:48实输出次数:8
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP48,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.05 ns
座面最大高度:2.8 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mmBase Number Matches:1

ICS9DB803DFT 数据手册

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DATASHEET  
ICS9DB803D  
Eight Output Differential Buffer for PCIe Gen 2  
Description  
Features/Benefits  
The 9DB803 is a DB800 Version 2.0 Yellow Cover part with PCI  
Express Gen II support. It can be used in PC or embedded  
systems to provide outputs that have low cycle-to-cycle jitter  
(50ps), low output-to-output skew (100ps), and are PCI Express  
Gen 2 compliant. The 9DB803 supports a 1 to 8 output  
configuration, taking a spread or non spread differential HCSL  
input from a CK410(B) main clock such as 954101 and  
932S401, or any other differential HCSL pair. 9DB803 can  
generate HCSL or LVDS outputs from 50 to 100MHz in PLL  
mode or 50 to 400Mhz in bypass mode. There are two de-  
jittering modes available selectable through the HIGH_BW#  
input pin, high bandwidth mode provides de-jittering for spread  
inputs and low bandwidth mode provides extra de-jittering for  
non-spread inputs. The SRC_IN#, PD#, and individual OE real-  
time input pins provide completely programmable power  
management control.  
Spread spectrum modulation tolerant, 0 to -0.5% down  
spread and +/- 0.25% center spread.  
Supports undriven differential outputs in PD# and  
SRC_STOP# modes for power management.  
Output Features  
8 - 0.7V current-mode differential output pairs  
Supports zero delay buffer mode and fanout mode  
Bandwidth programming available  
Key Specifications  
Outputs cycle-cycle jitter < 50ps  
Outputs skew: 50ps  
50-100 MHz operation in PLL mode  
50-400 MHz operation in Bypass mode  
Phase jitter: PCIe Gen1 < 86ps peak to peak  
Phase jitter: PCIe Gen2 < 3.1ps rms  
48-pin SSOP/TSSOP package  
Available in RoHS compliant packaging  
Funtional Block Diagram  
8
OE_(7:0)  
SPREAD  
COMPATIBLE  
PLL  
SRC_IN  
SRC_IN#  
M
U
X
8
STOP  
LOGIC  
DIF(7:0))  
SRC_STOP#  
HIGH_BW#  
CONTROL  
LOGIC  
BYPASS#/PLL  
PD#  
IREF  
SDATA  
SCLK  
LOCK  
Note: Polarities shown for OE_INV = 0.  
IDTTM/ICSTM Eight Output Differential Buffer for PCIe Gen 2  
ICS9DB803D  
REV B 08/23/07  
1

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