5秒后页面跳转
9P936AFLFT PDF预览

9P936AFLFT

更新时间: 2024-02-22 01:32:39
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管双倍数据速率
页数 文件大小 规格书
12页 190K
描述
Low Skew Dual Bank DDR I/II Fan-out Buffer

9P936AFLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.75
Is Samacsys:N系列:5V
输入调节:STANDARDJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:9.7 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER最大I(ol):0.03 A
湿度敏感等级:1功能数量:1
反相输出次数:1端子数量:28
实输出次数:1最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP28,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:1.8/2.5 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.04 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mm最小 fmax:125 MHz
Base Number Matches:1

9P936AFLFT 数据手册

 浏览型号9P936AFLFT的Datasheet PDF文件第2页浏览型号9P936AFLFT的Datasheet PDF文件第3页浏览型号9P936AFLFT的Datasheet PDF文件第4页浏览型号9P936AFLFT的Datasheet PDF文件第5页浏览型号9P936AFLFT的Datasheet PDF文件第6页浏览型号9P936AFLFT的Datasheet PDF文件第7页 
DATASHEET  
ICS9P936  
Low Skew Dual Bank DDR I/II Fan-out Buffer  
Description  
Pin Configuration  
Dual DDR I/II fanout buffer for VIA Chipset  
AVDD2.5  
AGND  
GND  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VDDQ2.5/1.8  
Output Features  
BUF_INT  
BUF_INC  
DDRT0  
DDRC0  
DDRT1  
DDRC1  
AVDD2.5  
AGND  
3
Low skew, fanout buffer  
4
SMBus for functional and output control  
Single bank 1-6 differential clock distribution  
1 pair of differential feedback pins for input to output  
synchronization  
DDRT5  
DDRC5  
5
6
GND  
7
Supports up to 2 DDR DIMMs  
VDDQ2.5/1.8  
DDRT4  
8
266MHz (DDRI 533) output frequency support  
400MHz (DDRII 800) output frequency support  
Programmable skew through SMBus  
GND  
9
VDDQ2.5/1.8  
DDRC4  
DDRT3  
10  
11  
12  
13  
14  
FB_OUTT  
FB_OUTC  
DDRT2  
Individual output control programmable through SMBus  
DDRC3  
SDATA  
SCLK  
DDRC2  
Key Specifications  
28-SSOP & TSSOP  
OUTPUT - OUTPUT skew: <100ps  
Output Rise and Fall Time for DDR outputs: 650ps - 950ps  
DUTY CYCLE: 47% - 53%  
28-pin SSOP/TSSOP package  
RoHS compliant packaging  
Funtional Block Diagram  
BUF_INC  
BUF_INT  
Control  
Logic  
SCLK  
FB_OUTC  
FB_OUTT  
SDATA  
DDRC (5:0)  
DDRT (5:0)  
IDTTM/ICSTM Low Skew Dual Bank DDR I/II Fan-out Buffer  
1084C 12/03/09  

与9P936AFLFT相关器件

型号 品牌 描述 获取价格 数据表
9P936AGLF IDT Low Skew Dual Bank DDR I/II Fan-out Buffer

获取价格

9P936AGLFT IDT Low Skew Dual Bank DDR I/II Fan-out Buffer

获取价格

9PAMF10 ADVANTECH Ready-to-use cabling call for custom lengths

获取价格

9PAMF15 ADVANTECH Ready-to-use cabling call for custom lengths

获取价格

9PAMF25 ADVANTECH Ready-to-use cabling call for custom lengths

获取价格

9PAMF6 ADVANTECH Ready-to-use cabling call for custom lengths

获取价格