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9FG1201HFLF PDF预览

9FG1201HFLF

更新时间: 2024-01-17 06:09:07
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路光电二极管PC
页数 文件大小 规格书
23页 241K
描述
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

9FG1201HFLF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.76
JESD-30 代码:R-PDSO-G56JESD-609代码:e3
长度:14 mm端子数量:56
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:400 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
主时钟/晶体标称频率:400 MHz座面最大高度:1.2 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:6.1 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

9FG1201HFLF 数据手册

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DATASHEET  
ICS9FG1201H  
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, &  
FBD  
Description  
Features/Benefits  
The ICS9FG1201H follows the Intel DB1200G Rev 1.0 Differential  
Buffer Specification. This buffer provides 12 output clocks for CPU  
Host Bus, PCI-Express, or Fully Buffered DIMM applications. The  
outputs are configured with two groups. Both groups (DIF 9:0) and  
(DIF 11:10) can be equal to or have a gear ratio to the input clock. A  
differential CPU clock from a CK410B or CK410B+ main clock  
generator, such as the ICS932S421, drives the ICS9FG1201. The  
ICS9FG1201H can provide outputs up to 400MHz  
Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)  
Power up default is all outputs in 1:1 mode  
DIF_(9:0) can be “gear-shifted” from the input CPU Host  
Clock  
DIF_(11:10) can be “gear-shifted” from the input CPU Host  
Clock  
Spread spectrum compatible  
Supports output clock frequencies up to 400 MHz  
8 Selectable SMBus addresses  
SMBus address determines PLL or Bypass mode  
Key Specifications  
DIF output cycle-to-cycle jitter < 50ps  
DIF output-to-output skew < 50ps within a group  
DIF output-to-output skew < 100ps across all outputs  
56-pin SSOP/TSSOP package  
RoHScompliantpackaging  
Functional Block Diagram  
OE#  
SPREAD  
COMPATIBLE  
PLL  
GEAR  
SHIFT  
LOGIC  
2
STOP  
DIF(11:10)  
LOGIC  
10  
OE(9:0)#  
SPREAD  
COMPATIBLE  
PLL  
GEAR  
SHIFT  
LOGIC  
CLK_IN  
10  
STOP  
DIF(9:0)  
LOGIC  
CLK_IN#  
HIGH_BW#  
FS_A_410  
VTT_PWRGD#/PD  
SMB_A0  
SMB_A1  
CONTROL  
LOGIC  
SMB_A2_PLLBYP#  
SMBDAT  
SMBCLK  
IREF  
IDTTM/ICSTM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD  
1371F — 09/23/09  
1

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