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9FG1200DG-1LFT

更新时间： 2024-01-13 08:11:46

品牌	Logo	应用领域
艾迪悌 - IDT		装置 PC 时钟
页数	文件大小	规格书
23页	288K
描述
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2

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9FG1200DG-1LFT 数据手册

DATASHEET

Frequency Gearing Clock for CPU, PCIe Gen1, Gen2

& FBD

ICS9FG1200D-1

Description

Features/Benefits

ICS9FG1200D-1 follows the Intel DB1200GS Differential Buffer

Specification. This buffer provides 12 output clocks for CPU Host

Bus, PCIe Gen2, or Fully Buffered DIMM applications.The outputs

are configured with two groups. Both groups (DIF 9:0) and (DIF

11:10) can be equal to or have a gear ratio to the input clock. A

differential CPU clock from a CK410B+ main clock generator,

such as the ICS932S421, drives the ICS9FG1200D-1. The

ICS9FG1200D-1 can provide outputs up to 400MHz.

•

Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)

Power up default is all outputs in 1:1 mode

DIF_(9:0) can be “gear-shifted” from the input CPU Host

Clock

•

DIF_(11:10) can be “gear-shifted” from the input CPU

Host Clock

•

Spread spectrum compatible

Supports output clock frequencies up to 400 MHz

8 Selectable SMBus addresses

SMBus address determines PLL or Bypass mode

Key Specifications

•

DIF output cycle-to-cycle jitter < 50ps

•

DIF output-to-output skew < 100ps across all outputs in 1:1

mode

•

56-pin SSOP/TSSOP package

RoHS compliant packaging

Functional Block Diagram

OE#

SPREAD

COMPATIBLE

1:1 PLL

STOP

DIF(11:10)

LOGIC

OE(9:0)#

SPREAD

COMPATIBLE

GEARING PLL

CLK_IN

STOP

DIF(9:0)

LOGIC

CLK_IN#

HIGH_BW#

FS_A_410

VTT_PWRGD#/PD

SMB_A0

SMB_A1

CONTROL

LOGIC

SMB_A2_PLLBYP#

SMBDAT

SMBCLK

IREF

IDT^®Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD

1138C 02/08/10

12 3 4 5 6 7...23

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