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9DB403DGLF PDF预览

9DB403DGLF

更新时间: 2024-01-01 14:02:04
品牌 Logo 应用领域
艾迪悌 - IDT PC
页数 文件大小 规格书
19页 278K
描述
Four Output Differential Buffer for PCIe Gen 1 and Gen 2

9DB403DGLF 数据手册

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DATASHEET  
ICS9DB403D  
Four Output Differential Buffer for PCIe Gen 1 and Gen 2  
Features/Benefits  
Description  
Spread spectrum modulation tolerant, 0 to -0.5% down  
spread and +/- 0.25% center spread.  
The ICS9DB403 is compatible with the Intel DB400v2 Differential  
Buffer Specification.This buffer provides 4 PCI-Express Gen2 clocks.  
The ICS9DB403 is driven by a differential output pair from a  
CK410B+, CK505 or CK509B main clock generator.  
Supports undriven differential outputs in PD# and  
SRC_STOP# modes for power management.  
Key Specifications  
Output Features  
4 - 0.7V current-mode differential output pairs  
Supports zero delay buffer mode and fanout mode  
Bandwidth programming available  
50-100 MHz operation in PLL mode  
50-400 MHz operation in Bypass mode  
Outputs cycle-cycle jitter < 50ps  
Outputs skew: 50ps  
Phase jitter: PCIe Gen1 < 86ps peak to peak  
Phase jitter: PCIe Gen2 < 3.0/3.1ps rms  
28-pin SSOP/TSSOP pacakge  
Available in RoHS compliant packaging  
Supports Commercial (0 to +70°C) and Industrial (-40 to  
+85°C) temperature ranges  
Functional Block Diagram  
2
-OE(6, 1)  
SPREAD  
COMPATIBLE  
PLL  
SRC_IN  
SRC_IN#  
4
M
STOP  
LOGIC  
DIF(6,5,2,1)  
U
X
PD  
BYPASS#/PLL  
SDATA  
CONTROL  
LOGIC  
SCLK  
IREF  
Note: Polarities shown for OE_INV = 0.  
IDTTM/ICSTM Four Output Differential Buffer for PCIe and Gen 1 and Gen 2  
ICS9DB403D  
REV L 10/07/09  
1

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