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9DB233AFILF PDF预览

9DB233AFILF

更新时间: 2024-02-23 19:46:22
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管PC
页数 文件大小 规格书
14页 197K
描述
Two Output Differential Buffer for PCIe Gen3

9DB233AFILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:3.94
Samacsys Description:TSSOP 4.4 MM 0.65MM PITCH系列:9DB
输入调节:DIFFERENTIALJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:6.5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:20实输出次数:2
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.05 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm

9DB233AFILF 数据手册

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DATASHEET  
Two Output Differential Buffer for PCIe Gen3  
Features/Benefits:  
9DB233  
Recommended Application:  
OE# pins/Suitable for Express Card applications  
2 output PCIe Gen3 zero-delay/fanout buffer  
PLL or bypass mode/PLL can dejitter incoming clock  
Selectable PLL bandwidth/minimizes jitter peaking in  
downstream PLL's  
General Description:  
The 9DB233 zero-delay buffer supports PCIe Gen3  
requirements, while being backwards compatible to PCIe  
Gen2 and Gen1. The 9DB233 is driven by a differential SRC  
output pair from an IDT 932S421 or 932SQ420 or equivalent  
main clock generator. It attenuates jitter on the input clock  
and has a selectable PLL bandwidth to maximize  
performance in systems with or without Spread-Spectrum  
clocking. An SMBus interface allows control of the PLL  
bandwidth and bypass options, while 2 clock request (OE#)  
pins make the 9DB233 suitable for Express Card  
applications.  
Spread Spectrum Compatible/tracks spreading input  
clock for low EMI  
SMBus Interface/unused outputs can be disabled  
Output Features:  
2 - 0.7V current mode differential output pairs (HCSL)  
Key Specifications:  
Cycle-to-cycle jitter < 50 ps  
Output-to-output skew < 50 ps  
PCIe Gen3 phase jitter < 1.0ps RMS  
Block Diagram  
OE0#  
OE1#  
DIF_0  
DIF_1  
SRC_IN  
SPREAD  
COMPATIBLE  
PLL  
SRC_IN#  
PLL_BW  
SMBDAT  
SMBCLK  
CONTROL  
LOGIC  
IREF  
IDT® Two Output Differential Buffer for PCIe Gen3  
1667C—04/20/11  
1

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