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9DB1933 PDF预览

9DB1933

更新时间: 2024-01-19 11:31:18
品牌 Logo 应用领域
艾迪悌 - IDT PC
页数 文件大小 规格书
17页 185K
描述
Nineteen Output Differential Buffer for PCIe Gen3

9DB1933 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:VFQFPN
包装说明:HVQCCN, LCC72,.39SQ,20针数:72
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.46
Samacsys Confidence:4Samacsys Status:Released
2D Presentation:https://componentsearchengine.com/2D/0T/11130259.2.1.pngSchematic Symbol:https://componentsearchengine.com/symbol.php?partID=11130259
PCB Footprint:https://componentsearchengine.com/footprint.php?partID=111302593D View:https://componentsearchengine.com/viewer/3D.php?partID=11130259
Samacsys PartID:11130259Samacsys Image:https://componentsearchengine.com/Images/9/9DB1933AKLFT.jpg
Samacsys Thumbnail Image:https://componentsearchengine.com/Thumbnails/2/9DB1933AKLFT.jpgSamacsys Pin Count:73
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Quad Flat No-Lead
Samacsys Footprint Name:72-Lead VFQFN--Samacsys Released Date:2020-01-27 12:32:07
Is Samacsys:N系列:9DB
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQCC-N72
JESD-609代码:e3长度:10 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:72实输出次数:19
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC72,.39SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.15 ns
座面最大高度:1 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

9DB1933 数据手册

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DATASHEET  
Nineteen Output Differential Buffer for PCIe Gen3  
9DB1933  
Recommended Application  
Features/Benefits  
8 Selectable SMBus Addresses/Mulitple devices can share  
the same SMBus Segment  
19 output PCIe Gen3 zero-delay/fanout buffer  
11 dedicated and 3 group OE# pins/Hardware control of the  
outputs  
General Description  
The 9DB1933 zero-delay buffer supports PCIe Gen3  
requirements, while being backwards compatible to PCIe Gen2  
and Gen1. The 9DB1933 is driven by a differential SRC output  
pair from an IDT 932S421, 932SQ420, or equivalent, main  
clock generator. It attenuates jitter on the input clock and has a  
selectable PLL bandwidth to maximize performance in systems  
with or without Spread-Spectrum clocking.  
PLL or bypass mode/PLL can dejitter incoming clock  
Selectable PLL bandwidth/minimizes jitter peaking in  
downstream PLL's  
Spread Spectrum Compatible/tracks spreading input clock  
for low EMI  
SMBus Interface/unused outputs can be disabled  
Supports undriven differential outputs in Power Down mode  
for power management  
Output Features  
19 - 0.7V current mode differential HCSL output pairs  
Key Specifications  
Cycle-to-cycle jitter <50ps  
Output-to-output skew < 150 ps  
PCIe Gen3 phase jitter < 1.0ps RMS  
Functional Block Diagram  
OE(17_18)#  
13  
OE(15_16)#  
OE(14:5)#,  
OE_01234#  
PLL  
(SS Compatible)  
DIF_IN  
DIF_IN#  
19  
DIF(18:0)  
HIGH_BW#  
CKPWRGD/PD#  
SMB_A0  
SMB_A1  
Logic  
SMB_A2_PLLBYP#  
SMBDAT  
SMBCLK  
IREF  
IDT® Nineteen Output Differential Buffer for PCIe Gen3  
1676A—07/12/10  
1

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