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89HPES8NT2 PDF预览

89HPES8NT2

更新时间: 2024-02-07 01:55:56
品牌 Logo 应用领域
艾迪悌 - IDT 开关PC
页数 文件大小 规格书
3页 54K
描述
8-Lane 2-Port Non-Transparent PCI Express㈢ Switch

89HPES8NT2 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:19 X 19 MM, 1 MM PITCH, GREEN, CABGA-324针数:324
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.72
地址总线宽度:总线兼容性:PCI
最大时钟频率:125 MHz外部数据总线宽度:
JESD-30 代码:S-PBGA-B324JESD-609代码:e1
长度:19 mm湿度敏感等级:3
端子数量:324最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA324,18X18,40
封装形状:SQUARE封装形式:GRID ARRAY, LOW PROFILE
峰值回流温度(摄氏度):260电源:1,3.3 V
认证状态:Not Qualified座面最大高度:1.5 mm
子类别:Bus Controllers最大供电电压:1.1 V
最小供电电压:0.9 V标称供电电压:1 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:19 mmuPs/uCs/外围集成电路类型:BUS CONTROLLER, PCI
Base Number Matches:1

89HPES8NT2 数据手册

 浏览型号89HPES8NT2的Datasheet PDF文件第2页浏览型号89HPES8NT2的Datasheet PDF文件第3页 
89HPES8NT2  
Product Brief  
8-Lane 2-Port Non-Transparent  
PCI Express® Switch  
Ability to load device configuration from serial EEPROM  
Ability to control device via SMBus  
Device Overview  
The 89HPES8NT2 is a member of the IDT PRECISE™ family of PCI  
Express® switching solutions offering the next-generation I/O intercon-  
nect standard. The PES8NT2 is a 8-lane, 2-port peripheral chip that  
provides high-performance switching and non-transparent bridging  
(NTB) functions between a PCIe® upstream port and an NTB down-  
stream port. The PES8NT2 is a part of the IDT PCIe System Intercon-  
nect Products and is intended to be used with IDT PCIe System  
Interconnect Switches. Together, the chipset targets multi-host and intel-  
ligent I/O applications such as communications, storage, and blade  
servers where inter-domain communication is required.  
Non-Transparent Port  
Crosslink support on NTB port  
Four mapping windows supported  
Each may be configured as a 32-bit memory or I/O window  
May be paired to form a 64-bit memory window  
Interprocessor communication  
Thirty-two inbound and outbound doorbells  
Four inbound and outbound message registers  
Two shared scratchpad registers  
Allows up to sixteen masters to communicate through the non-  
transparent port  
No limit on the number of supported outstanding transactions  
through the non-transparent bridge  
Completely symmetric non-transparent bridge operation  
allows similar/same configuration software to be run  
Supports direct connection to a transparent or non-transparent  
port of another switch  
Features  
High Performance PCI Express Switch  
Eight PCI Express lanes (2.5Gbps), two switch ports  
Delivers 32 Gbps (4 GBps) of aggregate switching capacity  
Low latency cut-through switch architecture  
Support for Max Payload size up to 2048 bytes  
Supports one virtual channel and eight traffic classes  
PCI Express Base specification Revision 1.0a compliant  
Highly Integrated Solution  
Requires no external components  
Incorporates on-chip internal memory for packet buffering and  
queueing  
Integrates eight 2.5 Gbps embedded full duplex SerDes, 8B/  
10B encoder/decoder (no separate transceivers needed)  
Flexible Architecture with Numerous Configuration Options  
Supports automatic per port link width negotiation (x8, x4, x2,  
or x1)  
Static lane reversal on all ports  
Automatic polarity inversion on all lanes  
Supports locked transactions, allowing use with legacy soft-  
ware  
Block Diagram  
2-Port Switch Core  
Port  
Arbitration  
Frame Buffer  
Route Table  
Scheduler  
Transaction Layer  
Data Link Layer  
Multiplexer / Demultiplexer  
Transaction Layer  
Data Link Layer  
Non-  
Transparent  
Bridge  
Multiplexer / Demultiplexer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
Phy  
Logical  
Layer  
...  
...  
SerDes SerDes  
SerDes  
SerDes SerDes  
SerDes  
8 PCI Express Lanes  
x4 Upstream Port and One x4 Downstream Port  
Figure 1 Internal Block Diagram  
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.  
1 of 3  
March 14, 2007  
© 2007 Integrated Device Technology, Inc.  

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