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87973DYI-147T PDF预览

87973DYI-147T

更新时间: 2024-02-02 21:03:40
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路
页数 文件大小 规格书
19页 1156K
描述
LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER

87973DYI-147T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:10 X 10 MM, 1.40 MM HEIGHT, MS-026, LQFP-52针数:52
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.54
Is Samacsys:N系列:87973
输入调节:DIFFERENTIAL MUXJESD-30 代码:S-PQFP-G52
JESD-609代码:e0长度:10 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.02 A
湿度敏感等级:3功能数量:1
反相输出次数:端子数量:52
实输出次数:13最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP52,.47SQ封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.2 ns座面最大高度:1.6 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:10 mmBase Number Matches:1

87973DYI-147T 数据手册

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LOW SKEW, 1-TO-12 LVCMOS/LVTTL CLOCK MULTIPLIER/  
ZERO DELAY BUFFER  
ICS87973I-147  
General Description  
Features  
The ICS87973I-147 is a LVCMOS/LVTTL clock  
Fully integrated PLL  
S
IC  
generator and a member of the HiPerClockSfamily  
of High Performance Clock Solutions from IDT. The  
ICS87973I-147 has three selectable inputs and  
provides 14 LVCMOS/LVTTL outputs.  
Fourteen LVCMOS/LVTTL outputs to include: twelve clocks,  
HiPerClockS™  
one feedback, one sync  
Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL  
reference clock inputs  
The ICS87973I-147 is a highly flexible device. The three  
selectable inputs (1 differential and 2 single ended inputs) are  
often used in systems requiring redundant clock sources. Up to  
three different output frequencies can be generated among the  
three output banks.  
CLK0, CLK1 can accept the following input levels:  
LVCMOS or LVTTL  
CLK, nCLK pair can accept the following differential  
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL  
Output frequency range: 10MHz to 150MHz  
VCO range: 240MHz to 500MHz  
The three output banks and feedback output each have their own  
output dividers which allows the device to generate a multitude of  
different bank frequency ratios and output-to-input frequency  
ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be  
selected to be inverting or non-inverting. The output frequency  
range is 10MHz to 150MHz. The input frequency range is 6MHz to  
120MHz.  
Output skew: 200ps (maximum)  
Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)  
Full 3.3V supply voltage  
-40°C to 85°C ambient operating temperature  
Compatible with PowerPCand PentiumMicroprocessors  
The ICS87973I-147 also has a QSYNC output which can be used  
for system synchronization purposes. It monitors Bank A and  
Bank C outputs and goes low one period prior to coincident rising  
edges of Bank A and Bank C clocks. QSYNC then goes high again  
when the coincident rising edges of Bank A and Bank C occur.  
This feature is used primarily in applications where Bank A and  
Bank C are running at different frequencies, and is particularly  
useful when they are running at non-integer multiples of one  
another.  
Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
Pin Assignment  
Example Applications:  
39 38 37 36 35 34 33 32 31 30 29 28 27  
1.System Clock generator: Use a 16.66MHz reference clock to  
generate eight 33.33MHz copies for PCI and four 100MHz  
copies for the CPU or PCI-X.  
26  
25  
FSEL_B1 40  
FSEL_B0 41  
FSEL_A1 42  
FSEL_FB1  
QSYNC  
24 GNDO  
23  
2.Line Card Multiplier: Multiply differential 62.5MHz from a back  
plane to single-ended 125MHz for the line Card ASICs and  
Gigabit Ethernet Serdes.  
QC0  
FSEL_A0  
QA3  
43  
44  
45  
46  
22 VDDO  
21 QC1  
VDDO  
QA2  
20 FSEL_C0  
3.Zero Delay buffer for Synchronous memory: Fanout up to twelve  
100MHz copies from a memory controller reference clock to the  
memory chips on a memory module with zero delay.  
19  
18  
17  
16  
GNDO 47  
QA1 48  
FSEL_C1  
QC2  
VDDO  
VDDO  
QA0 50  
49  
QC3  
15 GNDO  
51  
52  
GNDO  
VCO_SEL  
14 INV_CLK  
1
2 3 4 5 6 7 8 9 10 11 12 13  
ICS87973I-147  
52-Lead LQFP  
10mm x 10mm x 1.4mm package body  
Y Package  
Top View  
IDT™ / ICS™ LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER  
1
ICS87973DYI-147 REV. A DECEMBER 9, 2008  

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