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874005AG-04LFT PDF预览

874005AG-04LFT

更新时间: 2024-02-21 09:18:36
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器逻辑集成电路光电二极管衰减器PC
页数 文件大小 规格书
13页 274K
描述
PCI EXPRESS™ JITTER ATTENUATOR

874005AG-04LFT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-24针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:7.63
Is Samacsys:N系列:874005
输入调节:DIFFERENTIALJESD-30 代码:R-PDSO-G24
JESD-609代码:e3长度:7.8 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:24实输出次数:5
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm
最小 fmax:98 MHzBase Number Matches:1

874005AG-04LFT 数据手册

 浏览型号874005AG-04LFT的Datasheet PDF文件第2页浏览型号874005AG-04LFT的Datasheet PDF文件第3页浏览型号874005AG-04LFT的Datasheet PDF文件第4页浏览型号874005AG-04LFT的Datasheet PDF文件第5页浏览型号874005AG-04LFT的Datasheet PDF文件第6页浏览型号874005AG-04LFT的Datasheet PDF文件第7页 
PCI EXPRESS™ JITTER ATTENUATOR  
ICS874005-04  
GENERAL DESCRIPTION  
FEATURES  
The ICS874005-04 is a high performance Diff-  
Five differential LVDS output pairs  
ICS  
erential-to-LVDS Jitter Attenuator designed for use  
in PCI Express systems. In some PCI Express  
systems, such as those found in desktop PCs, the  
PCI Express clocks are generated from a low  
One differential clock input  
HiPerClockS™  
Supports 100MHz, 125MHz, and 250MHz Serdes reference  
clocks  
bandwidth, high phase noise PLL frequency synthesizer. In  
these systems, a jitter attenuator may be required to attenuate  
high frequency random and deterministic jitter components from  
the PLL synthesizer and from the system board. The  
ICS874005-04 has 2 PLL bandwidth modes: 300kHz and  
2MHz. The 300kHz mode will provide maximum jitter  
attenuation, but higher PLL tracking skew and spread spectrum  
modulation from the motherboard synthesizer may be  
attenuated. The 2MHz bandwidth provides the best tracking  
skew and will pass most spread profiles. The ICS874005-04  
supports Serdes reference clock frequencies of 100MHz,  
125MHz and 250MHz.  
CLK and nCLK supports the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
Output frequency range: 98MHz - 320MHz  
Input frequency range: 98MHz - 128MHz  
• PCI Express (2.5 Gb/S) and Gen 2 (5 Gb/s) jitter compliant  
RMS phase jitter @ 100MHz (1.875MHz – 20MHz):  
0.88ps (typical)  
VCO range: 490MHz - 640MHz  
Cycle-to-cycle jitter: 35ps (maximum) QA = QB = ÷4  
3.3V operating supply  
The ICS874005-04 uses IDT’s 3rd Generation FemtoClockTM  
PLL technology to achive the lowest possible phase noise.  
The device is packaged in a 24 Lead TSSOP package, making  
it ideal for use in space constrained applications such as PCI  
Express add-in cards.  
Two bandwidth modes allow the system designer to make  
jitter attenuation/tracking skew design trade-offs  
0°C to 70°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
PLL BANDWIDTH  
BW_SEL  
0 = PLL Bandwidth: ~300kHz (default)  
1 = PLL Bandwidth: ~2MHz  
BLOCK DIAGRAM  
Pullup  
OEA  
Pulldown  
Pulldown  
F_SELA  
BW_SEL  
QA0  
PIN ASSIGNMENT  
F_SELA  
0 = ~300kHz  
1 = ~2MHz  
0
1
÷5 (default)  
÷4  
nQA0  
1
2
3
4
nQB2  
nQA1  
QA1  
24  
23  
22  
21  
20  
19  
18  
QB2  
VDDO  
QB1  
nQB1  
QA1  
Pulldown  
Pullup  
CLK  
Phase  
Detector  
VCO  
VDDO  
nQA1  
QB0  
490 - 640MHz  
nCLK  
5
6
7
8
QA0  
nQA0  
MR  
QB0  
nQB0  
F_SELB  
OEB  
F_SELB  
0
1
÷2 (default)  
÷4  
BW_SEL  
VDDA  
17  
16  
15  
14  
13  
nQB0  
QB1  
9
GND  
GND  
nCLK  
CLK  
M = ÷5 (fixed)  
10  
11  
12  
F_SELA  
VDD  
nQB1  
QB2  
OEA  
ICS874005-04  
24-Lead TSSOP  
nQB2  
Pulldown  
F_SELB  
MR  
4.40mm x 7.8mm x 0.925mm package body  
Pulldown  
Pullup  
G Package  
Top View  
OEB  
IDT/ ICSPCI EXPRESS™ JITTER ATTENUATOR  
1
ICS874005AG-04 REV. A JULY 29, 2008  

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