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8344BYT PDF预览

8344BYT

更新时间: 2024-01-26 04:05:12
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
18页 136K
描述
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

8344BYT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP, QFP48,.35SQ,20针数:48
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
系列:8344输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQFP-G48JESD-609代码:e0
长度:7 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.036 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:48实输出次数:24
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP48,.35SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):240电源:2.5/3.3 V
Prop。Delay @ Nom-Sup:4.5 ns传播延迟(tpd):4.3 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.275 ns
座面最大高度:1.6 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:20
宽度:7 mmBase Number Matches:1

8344BYT 数据手册

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ICS8344  
LOW SKEW, 1-TO-24  
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER  
GENERAL DESCRIPTION  
FEATURES  
The ICS8344 is a low voltage, low skew, 1-to-24 Differential-  
to-LVCMOS Fanout Buffer.The ICS8344 is designed to trans-  
late any differential signal levels to LVCMOS levels. The low  
impedance LVCMOS outputs are designed to drive 50Ω se-  
ries or parallel terminated transmission lines. The effective  
fanout can be increased to 48 by utilizing the ability of the  
outputs to drive two series terminated lines. Redundant clock  
applications can make use of the dual clock input. The dual  
clock inputs also facilitate board level testing. ICS8344 is  
characterized at full 3.3V, full 2.5V and mixed 3.3V input and  
2.5V output operating supply modes.  
Twenty-four LVCMOS outputs, 7Ω typical output impedance  
Selectable differential clock input pairs for redundant  
clock applications  
CLKx, nCLKx pairs can accept the following differential  
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL  
Maximum output frequency: 167MHz  
Translates any differential input signal (LVPECL, LVHSTL,  
LVDS) to LVCMOS without external bias networks  
Translates any single-ended input signal to LVCMOS  
with resistor bias on nCLK input  
Guaranteed output and part-to-part skew characteristics  
make the ICS8344 ideal for those clock distribution applica-  
tions demanding well defined performance and repeatability.  
Multiple output enable pins for disabling unused outputs  
in reduced fanout applications  
Output skew: 275ps (maximum)  
Part-to-part skew: 600ps (maximum)  
Bank skew: 150ps (maximum)  
Propagation Delay: 4.3ns (maximum)  
3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes  
0°C to 70°C ambient operating temperature  
Available in standard (RoHS 5) and lead-free (RoHS 6)  
packages  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
CLK_SEL  
48 47 46 45 44 43 42 41 40 39 38 37  
Q16  
Q17  
VDDO  
GND  
Q18  
Q19  
Q20  
Q21  
VDDO  
GND  
Q22  
Q23  
1
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
Q7  
CLK0  
nCLK0  
2
Q6  
0
3
VDDO  
GND  
Q5  
CLK1  
1
nCLK1  
4
5
Q0:Q7  
6
Q4  
ICS8344  
7
Q3  
OE1  
8
Q2  
O8:Q15  
9
VDDO  
GND  
Q1  
10  
11  
12  
OE2  
O16:Q23  
Q0  
13 14 15 16 17 18 19 20 21 22 23 24  
OE3  
48-Lead LQFP  
7mm x 7mm x 1.4mm package body  
Y Package  
TopView  
8344BY  
1
REV.A JANUARY 5, 2011  

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