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71V433S12PF PDF预览

71V433S12PF

更新时间: 2024-01-31 09:55:04
品牌 Logo 应用领域
艾迪悌 - IDT 存储静态存储器
页数 文件大小 规格书
19页 263K
描述
32K x 32 3.3V Synchronous SRAM Flow-Through Outputs

71V433S12PF 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:QFP, QFP100,.63X.87针数:100
Reach Compliance Code:not_compliant风险等级:5.92
Is Samacsys:NBase Number Matches:1

71V433S12PF 数据手册

 浏览型号71V433S12PF的Datasheet PDF文件第2页浏览型号71V433S12PF的Datasheet PDF文件第3页浏览型号71V433S12PF的Datasheet PDF文件第4页浏览型号71V433S12PF的Datasheet PDF文件第5页浏览型号71V433S12PF的Datasheet PDF文件第6页浏览型号71V433S12PF的Datasheet PDF文件第7页 
IDT71V433  
32K x 32  
3.3V Synchronous SRAM  
Flow-Through Outputs  
Features  
32K x 32 memory configuration  
The IDT71V433 SRAM contains write, data-input, address and  
controlregisters.Therearenoregisters inthedataoutputpath(flow-  
througharchitecture). Internallogicallows the SRAMtogenerate a  
self-timed write based upon a decision which can be left until the  
extreme end of the write cycle.  
The burstmode feature offers the highestlevelofperformance to  
thesystemdesigner,astheIDT71V433canprovidefourcyclesofdata  
forasingleaddresspresentedtotheSRAM. Aninternalburstaddress  
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe  
access sequence.Thefirstcycleofoutputdatawillflow-throughfrom  
the arrayaftera clock-to-data access time delayfromthe risingclock  
edgeofthesamecycle. Ifburstmodeoperationisselected(ADV=LOW),  
the subsequent three cycles of output data will be available to the  
user on the next three rising clock edges. The order of these three  
addresses willbe definedbythe internalburstcounterandthe LBO  
inputpin.  
Supports high performance system speed:  
CommercialandIndustrial:  
— 11 11ns Clock-to-DataAccess (50MHz)  
— 12 12ns Clock-to-DataAccess (50MHz)  
LBO input selects interleaved or linear burst mode  
Self-timed write cycle with global write control (GW), byte  
write enable (BWE), and byte writes (BWx)  
Power down controlled by ZZ input  
Single 3.3V power supply (+10/-5%)  
Packaged in a JEDEC Standard 100-pin rectangular plastic  
thin quad flatpack (TQFP).  
Description  
The IDT71V433 is a 3.3V high-speed 1,048,576-bit SRAM orga-  
nized as 32K x 32 with full support of various processor interfaces  
includingthePentium™andPowerPC.Theflow-throughburstarchi-  
tectureprovidescost-effective2-1-1-1performanceforprocessorsupto  
50MHz.  
The IDT71V433 SRAM utilizes IDT's high-performance 3.3V  
CMOSprocess,andispackagedinaJEDECStandard14mmx20mm  
100-pinthinplasticquadflatpack(TQFP).  
PinDescription  
A0A14  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enable  
CE  
CS0, CS1  
OE  
Chips Selects  
Output Enable  
Global Write Enable  
Byte Write Enable  
GW  
BWE  
Individual Byte Write Selects  
Clock Input  
BW1BW4  
CLK  
Burst Address Advance  
Address Status (Cache Controller)  
Address Status (Processor)  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Synchronous  
Synchronous  
DC  
ADV  
ADSC  
ADSP  
LBO  
ZZ  
Asynchronous  
Synchronous  
N/A  
I/O0I/O31  
VDD, VDDQ  
VSS, VSSQ  
Data Input/Output  
Core and I/O Power Supply (3.3V)  
Array Ground, I/O Ground  
Power  
Power  
N/A  
3729 tbl 01  
PentiumisatrademarkofIntelCorp.  
PowerPCisatrademarkofInternationalBusinessMachines,Inc.  
AUGUST 2001  
1
DSC-3729/04  
©2000IntegratedDeviceTechnology,Inc.  

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