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70V7599S166BCI PDF预览

70V7599S166BCI

更新时间: 2024-02-02 09:03:26
品牌 Logo 应用领域
艾迪悌 - IDT 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
22页 225K
描述
HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE

70V7599S166BCI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:PQFP
包装说明:28 X 28 MM, 3.50 MM HEIGHT, PLASTIC, QFP-208针数:208
Reach Compliance Code:not_compliantECCN代码:3A991
HTS代码:8542.32.00.41风险等级:5.33
Is Samacsys:N最长访问时间:12 ns
其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE最大时钟频率 (fCLK):166 MHz
I/O 类型:COMMONJESD-30 代码:S-PQFP-G208
JESD-609代码:e0长度:28 mm
内存密度:4718592 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:36湿度敏感等级:3
功能数量:1端口数量:2
端子数量:208字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:FQFP
封装等效代码:QFP208,1.2SQ,20封装形状:SQUARE
封装形式:FLATPACK, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:2.5/3.3,3.3 V
认证状态:Not Qualified座面最大高度:4.1 mm
最大待机电流:0.04 A最小待机电流:3.15 V
子类别:SRAMs最大压摆率:0.83 mA
最大供电电压 (Vsup):3.45 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:28 mm
Base Number Matches:1

70V7599S166BCI 数据手册

 浏览型号70V7599S166BCI的Datasheet PDF文件第2页浏览型号70V7599S166BCI的Datasheet PDF文件第3页浏览型号70V7599S166BCI的Datasheet PDF文件第4页浏览型号70V7599S166BCI的Datasheet PDF文件第5页浏览型号70V7599S166BCI的Datasheet PDF文件第6页浏览型号70V7599S166BCI的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V 128K x 36  
SYNCHRONOUS  
BANK-SWITCHABLE  
IDT70V7599S  
DUAL-PORT STATIC RAM  
WITH 3.3V OR 2.5V INTERFACE  
Š
Features:  
– 1.5ns setup to clock and 0.5ns hold on all control, data, and  
address inputs @ 200MHz  
Data input, address, byte enable and control registers  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
LVTTL- compatible, 3.3V (±150mV) power supply  
for core  
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V  
(±100mV) power supply for I/Os and control signals on  
each port  
Industrial temperature range (-40°C to +85°C) is  
available at 166MHz and 133MHz  
Available in a 208-pin Plastic Quad Flatpack (PQFP),  
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball  
GridArray(BGA)  
128K x 36 Synchronous Bank-Switchable Dual-ported  
SRAM Architecture  
64 independent 2K x 36 banks  
– 4 megabits of memory on chip  
Bank access controlled via bank address pins  
High-speed data access  
– Commercial:3.4ns (200MHz)/3.6ns (166MHz)/  
4.2ns (133MHz) (max.)  
Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)  
Selectable Pipelined or Flow-Through output mode  
Counter enable and repeat features  
Dual chip enables allow for depth expansion without  
additional logic  
Full synchronous operation on both ports  
– 5ns cycle time, 200MHzoperation(14Gbps bandwidth)  
– Fast 3.4ns clock to data out  
Supports JTAG features compliant with IEEE 1149.1  
FunctionalBlockDiagram  
PL/FT  
L
PL/FT  
OPT  
CLK  
ADS  
CNTEN  
REPEAT  
R/W  
CE0R  
CE1R  
BE3R  
BE2R  
BE1R  
BE0R  
R
OPT  
L
R
CLK  
L
R
ADS  
L
R
CNTEN  
REPEAT  
R/W  
L
R
L
R
L
R
MUX  
CE0L  
CE1L  
BE3L  
BE2L  
BE1L  
BE0L  
CONTROL  
LOGIC  
CONTROL  
LOGIC  
2Kx36  
MEMORY  
ARRAY  
(BANK 0)  
OEL  
OER  
MUX  
MUX  
I/O  
CONTROL  
I/O  
CONTROL  
I/O0L-35L  
I/O0R-35R  
2Kx36  
MEMORY  
ARRAY  
A
10R  
0R  
(BANK 1)  
A
10L  
ADDRESS  
DECODE  
ADDRESS  
DECODE  
A
A
0L  
MUX  
BA5R  
BA4R  
BA3R  
BA2R  
BA1R  
BA0R  
BA5L  
BA4L  
BA3L  
BA2L  
BA1L  
BA0L  
BANK  
DECODE  
BANK  
DECODE  
MUX  
2Kx36  
MEMORY  
ARRAY  
(BANK 63)  
NOTE:  
MUX  
1. The Bank-Switchable dual-port uses a true SRAM  
core instead of the traditional dual-port SRAM core.  
As a result, it has unique operating characteristics.  
Please refer to the functional description on page 19  
for details.  
,
5626 drw 01  
TMS  
TCK  
TRST  
TDI  
TDO  
JTAG  
JANUARY 2009  
1
DSC 5626/6  
©2009IntegratedDeviceTechnology,Inc.  

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