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709179L9PFI PDF预览

709179L9PFI

更新时间: 2024-01-27 06:16:50
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
15页 180K
描述
HIGH-SPEED 32K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

709179L9PFI 数据手册

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PRELIMINARY  
HIGH-SPEED 32K x 9  
IDT709179L  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
ꢀeatures  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:7.5/9/12ns (max.)  
Industrial:9ns (max)  
additional logic  
Full synchronous operation on both ports  
4ns setup to clock and 0ns hold on all control, data, and  
address inputs  
Data input, address, and control registers  
Fast 7.5ns clock to data out in the Pipelined output mode  
Self-timed write allows fast cycle time  
Low-power operation  
IDT709179L  
Active: 1.2W (typ.)  
Standby: 2.5mW (typ.)  
Flow-Through or Pipelined output mode on either Port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
12ns cycle time, 83MHz operation in Pipelined output mode  
TTL- compatible, single 5V (±10%) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Available in a 100-pin Thin Quad Flatpack (TQFP) package  
ꢀunctional Block Diagram  
R/WR  
OER  
R/WL  
OEL  
CE0R  
CE1R  
CE0L  
CE1L  
1
1
0
0
0/1  
0/1  
0
0
1
1
/PIPEL  
FT  
0/1  
0/1  
FT/PIPER  
I/O0R - I/O8R  
I/O0L - I/O8L  
I/O  
Control  
I/O  
Control  
A14L  
A14R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A0R  
A0L  
CLKR  
CLKL  
ADSR  
ADSL  
CNTENL  
CNTENR  
CNTRSTR  
CNTRSTL  
5644 drw 01  
AUGUST 2001  
1
DSC-5644/1  
©2001IntegratedDeviceTechnology,Inc.  

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