5V49EE702NDGI

更新时间： 2024-01-18 17:06:02

品牌	Logo	应用领域
艾迪悌 - IDT		时钟驱动器时钟发生器逻辑集成电路 PC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
34页	702K
描述
EEPROM PROGRAMMABLE CLOCK GENERATOR

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技术参数
数据手册

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5V49EE702NDGI 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Not Recommended	零件包装代码：	VFQFPN
包装说明：	HVQCCN,	针数：	28
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	8.08
Samacsys Confidence：	3	Samacsys Status：	Released
2D Presentation：	https://componentsearchengine.com/2D/0T/11129626.2.1.png	Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=11129626
PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=11129626	3D View：	https://componentsearchengine.com/viewer/3D.php?partID=11129626
Samacsys PartID：	11129626	Samacsys Image：	https://componentsearchengine.com/Images/9/5V49EE702NDGI.jpg
Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/2/5V49EE702NDGI.jpg	Samacsys Pin Count：	29
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Quad Flat No-Lead
Samacsys Footprint Name：	28-pin 4mm x 4mm QFN)	Samacsys Released Date：	2020-01-22 13:06:28
Is Samacsys：	N	系列：	5V
输入调节：	MUX	JESD-30 代码：	S-XQCC-N28
JESD-609代码：	e3	长度：	4 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	湿度敏感等级：	1
功能数量：	1	反相输出次数：
端子数量：	28	实输出次数：	6
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.075 ns
座面最大高度：	1 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	NO LEAD
端子节距：	0.4 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	4 mm
最小 fmax：	500 MHz	Base Number Matches：	1

5V49EE702NDGI 数据手册

DATASHEET

EEPROM PROGRAMMABLE CLOCK GENERATOR

IDT5V49EE702

Description

Features:

The IDT5V49EE702 is a programmable clock generator

intended for high performance data-communications,

telecommunications, consumer, and networking

applications. There are four internal PLLs, each individually

programmable, allowing for four unique non-integer-related

frequencies. The frequencies are generated from a single

reference clock. The reference clock can come from one of

the two redundant clock inputs. A glitchless automatic or

manual switchover function allows any one of the redundant

clocks to be selected during normal operation.

• Four internal PLLs

• Internal non-volatile EEPROM

• Fast (400kHz) mode I C serial interface

• Input frequency range: 1 MHz to 200 MHz

• Output frequency range: 4.9 kHz to 500 MHz

• Reference crystal input with programmable linear load

capacitance

– Crystal frequency range: 8 MHz to 50 MHz

The IDT5V49EE702 is in-system, programmable and can

be programmed through the use of I C interface. An

internal EEPROM allows the user to save and restore the

configuration of the device without having to reprogram it on

power-up.

• Three independently controlled VDDO (1.8V - 3.3V)

• Each PLL has a 7-bit reference divider and a 12-bit

feedback-divider

• 8-bit output-divider blocks

• Fractional division capability on one PLL

Each of the four PLLs has an 7-bit reference divider and a

12-bit feedback divider. This allows the user to generate

four unique non-integer-related frequencies. The PLL loop

bandwidth is programmable to allow the user to tailor the

PLL response to the application. For instance, the user can

tune the PLL parameters to minimize jitter generation or to

maximize jitter attenuation. Spread spectrum generation

and/or fractional divides are allowed on two of the PLLs.

• Two of the PLLs support spread spectrum generation

capability

• I/O Standards:

– Outputs - 1.8 - 3.3 V LVTTL/ LVCMOS

– Outputs - LVPECL, LVDS and HCSL

– Inputs - 3.3 V LVTTL/ LVCMOS

• Programmable slew rate control

• Programmable loop bandwidth

• Programmable output inversion to reduce bimodal jitter

There are a total of five 8-bit output dividers. Each output

bank can be configured to support LVTTL, LVPECL, LVDS

or HCSL logic levels. Out0 (Output 0) supports LVTTL

standard only. The outputs are connected to the PLLs via a

switch matrix. The switch matrix allows the user to route the

PLL outputs to any output bank. This feature can be used to

simplify and optimize the board layout. In addition, each

output's slew rate and enable/disable function is

programmable.

• Redundant clock inputs with glitchless auto and manual

switchover options

• Individual output enable/disable

• Power-down mode

• 3.3V core V

• Available in VFQFPN package

• -40 to +85 C Industrial Temp operation

IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR

IDT5V49EE702 REV F 022310

12 3 4 5 6 7...34

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