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5V19EE604NDGI PDF预览

5V19EE604NDGI

更新时间: 2024-02-02 04:44:45
品牌 Logo 应用领域
艾迪悌 - IDT 时钟驱动器时钟发生器逻辑集成电路石英晶振压控振荡器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
29页 652K
描述
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR

5V19EE604NDGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:VFQFPN
包装说明:QFN-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
系列:5V输入调节:MUX
JESD-30 代码:S-XQCC-N28JESD-609代码:e3
长度:4 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:28
实输出次数:5最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.075 ns座面最大高度:1 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:NO LEAD端子节距:0.4 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:4 mm最小 fmax:200 MHz
Base Number Matches:1

5V19EE604NDGI 数据手册

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DATASHEET  
EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR  
IDT5V19EE604  
Description  
Features  
The IDT5V19EE604 is a programmable clock generator  
intended for high performance data-communications,  
telecommunications, consumer, and networking  
applications. There are four internal PLLs, each individually  
programmable, allowing for four unique non-integer-related  
frequencies. The frequencies are generated from a single  
reference clock. The reference clock can come from one of  
the two redundant clock inputs. A glitchless automatic or  
manual switchover function allows any one of the redundant  
clocks to be selected during normal operation.  
Four internal PLLs  
Internal non-volatile EEPROM  
2
Fast (400kHz) mode I C serial interface  
Input frequency range: 1 MHz to 200 MHz  
Output frequency range: 4.9 kHz to 200 MHz  
Reference crystal input with programmable linear load  
capacitance  
– Crystal frequency range: 8 MHz to 50 MHz  
The IDT5V19EE604 is in-system, programmable and can  
be programmed through the use of I C interface. An  
internal EEPROM allows the user to save and restore the  
configuration of the device without having to reprogram it on  
power-up.  
Integrated VCXO  
2
Three independently controlled VDDO (1.8V - 3.3V)  
Each PLL has a 7-bit reference divider and a 12-bit  
feedback-divider  
8-bit output-divider blocks  
Each of the four PLLs has an 7-bit reference divider and a  
12-bit feedback divider. This allows the user to generate  
four unique non-integer-related frequencies. The PLL loop  
bandwidth is programmable to allow the user to tailor the  
PLL response to the application. For instance, the user can  
tune the PLL parameters to minimize jitter generation or to  
maximize jitter attenuation. Spread spectrum generation  
and/or fractional divides are allowed on two of the PLLs.  
Fractional division capability on one PLL  
Two of the PLLs support spread spectrum generation  
capability  
I/O Standards:  
– Outputs - 1.8 - 3.3 V LVTTL/ LVCMOS  
– Inputs - 3.3 V LVTTL/ LVCMOS  
Programmable slew rate control  
Programmable loop bandwidth  
Programmable output inversion to reduce bimodal jitter  
There are a total of five 8-bit output dividers.The outputs are  
connected to the PLLs via a switch matrix. The switch  
matrix allows the user to route the PLL outputs to any  
output bank. This feature can be used to simplify and  
optimize the board layout. In addition, each output's slew  
rate and enable/disable function is programmable.  
Redundant clock inputs with glitchless auto and manual  
switchover options  
Individual output enable/disable  
Power-down mode  
3.3V core V  
DD  
Available in VFQFPN package  
-40 to +85 C Industrial Temp operation  
IDT® EEPROM PROGRAMMABLE VCXO CLOCK GENERATOR  
1
IDT5V19EE604 REV F 022310  

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