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542MILF

更新时间: 2024-01-24 11:35:53
品牌 Logo 应用领域
艾迪悌 - IDT 时钟
页数 文件大小 规格书
6页 171K
描述
CLOCK DIVIDER

542MILF 数据手册

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DATASHEET  
CLOCK DIVIDER  
ICS542  
Description  
Features  
The ICS542 is cost effective way to produce a high-quality  
clock output divided from a clock input. The chip accepts a  
clock input up to 156 MHz at 3.3 V and produces a divide by  
2, 4, 6, 8, 12, or 16 of the input clock. There are two outputs  
on the chip, one being a low-skew divide by two of the other.  
8-pin SOIC package, Pb free  
Available in RoHS compliant package  
IDT’s lowest cost clock divider  
Low skew (500 ps) outputs. One is /2 of the other  
Easy to use with other generators and buffers  
Input clock frequency up to 156 MHz  
Output clock duty cycle of 45/55  
Power-down turns off chip  
For instance, if an 100 MHz input clock is used, the ICS542  
can produce low-skew 50 MHz and 25 MHz clocks, or low  
skew 25 MHz and 12.5 MHz clocks. The chip has an  
all-chip power-down mode that stops the outputs low, and  
an OE pin that tri-states the outputs.  
Output Enable  
See the ICS541 and ICS543 for other clock dividers, and  
the ICS501, 502, 511, 512, and 525 for clock multipliers.  
Advanced, low-power CMOS process  
Operating voltage of 3.3 V or 5 V  
Does not degrade phase noise - no PLL  
Available in industrial and commercial temperature  
ranges  
Block Diagram  
VDD  
CLK1  
S1, S0  
Divider  
and  
/2  
Selection  
Circuitry  
CLK2  
Input Clock  
OE (both outputs)  
GND  
IDT™ / ICS™ CLOCK DIVIDER  
1
ICS542  
REV J 051310  

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