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502MLF

更新时间: 2024-01-17 20:26:05
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路光电二极管PC
页数 文件大小 规格书
7页 182K
描述
LOCO™ PLL CLOCK MULTIPLIER

502MLF 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.150 INCH, SOIC-8
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.23其他特性:ALSO OPERATES AT 3.3V SUPPLY
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm湿度敏感等级:1
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:190 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
主时钟/晶体标称频率:50 MHz认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER

502MLF 数据手册

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DATASHEET  
LOCO™ PLL CLOCK MULTIPLIER  
ICS502  
Description  
Features  
TM  
The ICS502 LOCO is the most cost effective way to  
Packaged as 8-pin SOIC or die  
Pb (lead) free package  
IDT’s lowest cost PLL clock  
Zero ppm multiplication error  
Easy to cascade with ICS5xx series  
Input crystal frequency of 5 – 27 MHz  
Input clock frequency of 2 – 50 MHz  
Output clock frequencies up to 190 MHz  
Low jitter – 50 ps one sigma  
Compatible with all popular CPUs  
Duty cycle of 45/55 up to 160 MHz  
Operating voltages of 3.0 to 5.5 V  
25 mA drive capability at TTL levels  
Industrial temperature version available  
Advanced, low-power CMOS process  
generate a high-quality, high-frequency clock output and a  
reference from a lower frequency crystal or clock input. The  
name LOCO stands for Low Cost Oscillator, as it is  
designed to replace crystal oscillators in most electronic  
systems. Using Phase-Locked Loop (PLL) techniques, the  
device uses a standard fundamental mode, inexpensive  
crystal to produce output clocks up to 160 MHz.  
Stored in the chip’s ROM is the ability to generate six  
different multiplication factors, allowing one chip to output  
many common frequencies (see table on page 2).  
This product is intended for clock generation. It has low  
output jitter (variation in the output period), but input to  
output skew and jitter are not defined or guaranteed. For  
applications which require defined input to output skew, use  
the ICS570B.  
Block Diagram  
VDD  
PLL Clock  
CLK  
Multiplier  
Circuitry and  
ROM  
2
S1, S0  
X1/ICLK  
Crystal or  
Crystal  
Clock input  
OScillator  
REF  
X2  
GND  
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER  
1
ICS502  
REV M 051310  

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