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308RIT PDF预览

308RIT

更新时间: 2024-01-25 09:22:55
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
9页 190K
描述
Clock Generator, 200MHz, PDSO20, 0.150 INCH, SSOP-20

308RIT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SSOP包装说明:SSOP, SSOP20,.25
针数:20Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.73JESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:8.65 mm
湿度敏感等级:1端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):225电源:3.3 V
主时钟/晶体标称频率:50 MHz认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Clock Generators
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

308RIT 数据手册

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DATASHEET  
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER  
ICS308  
Description  
Features  
The ICS308 is a versatile serially programmable, quad  
PLL clock source. The ICS308 can generate any  
frequency from 250 kHz to 200 MHz, and up to 6  
different output frequencies simultaneously. The  
outputs can be reprogrammed on the fly, and will lock to  
a new frequency in 10 ms or less. Smooth transitions  
(in which the clock duty cycle remains roughly 50%) are  
guaranteed if the output divider is not changed.  
Packaged in 20-pin SSOP (QSOP)  
Available in Pb (lead) free package  
Operating voltage of 3.3 V  
Highly accurate frequency generation  
M/N Multiplier PLL: M = 1..2048, N = 1..1024  
Serially programmable: user determines the output  
frequency via a 3-wire interface  
The device includes a PDTS pin which tri-states the  
output clocks and powers down the entire chip.  
Eliminates need for custom quartz oscillators  
Input crystal frequency of 5 - 27 MHz  
Optional programmable on-chip crystal capacitors  
Output clock frequencies up to 200 MHz  
Reference clock output  
The ICS308 default for non-programmed start-up are  
buffered reference clock outputs on all clock output  
pins.  
Power down tri-state mode  
Very low jitter  
NOTE: EOL for non-green parts to occur on  
5/13/10 per PDN U-09-01  
Block Diagram  
3
VDD  
CLK1  
CLK2  
PLL1  
PLL2  
PLL3  
PLL4  
STROBE  
SCLK  
CLK3  
Divide  
Logic  
and  
Output  
Enable  
Control  
CLK4  
DATA  
CLK5  
CLK6  
CLK7  
CLK8  
CLK9  
Crystal or  
clock input  
X1/ICLK  
Crystal  
Oscillator  
X2  
GND  
2
External capacitors are  
required with a crystal input.  
PDTS  
IDT™ / ICS™ SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER 1  
ICS308  
REV K 090209  

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