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307M-02IT PDF预览

307M-02IT

更新时间: 2024-02-03 14:39:56
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
10页 248K
描述
Clock Generator, 200MHz, PDSO16, 0.150 INCH, SOIC-16

307M-02IT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.150 INCH, SOIC-16
针数:16Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.64JESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
湿度敏感等级:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:3.3/5 V主时钟/晶体标称频率:50 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Clock Generators最大供电电压:5.5 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL宽度:3.9 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

307M-02IT 数据手册

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DATASHEET  
SERIALLY PROGRAMMABLE CLOCK SOURCE  
ICS307-01/-02  
Description  
Features  
The ICS307-01 and ICS307-02 are versatile serially  
programmable clock sources which take up very little  
board space. They can generate any frequency from 6  
to 200 MHz and have a second configurable output.  
The outputs can be reprogrammed on the fly and will  
lock to a new frequency in 10 ms or less. Smooth  
transitions (in which the clock duty cycle remains near  
50%) are guaranteed if the output divider is not  
changed.  
Packaged in 16-pin (150 mil wide) SOIC  
ICS307M-02 and -02I available in Pb (lead) free  
package  
Highly accurate frequency generation  
Serially programmable: user determines the output  
frequency via a 3 wire interface  
Eliminates need for custom quartz  
Input crystal frequency of 5 - 27 MHz  
Output clock frequencies up to 200 MHz  
Power down tri-state mode  
The devices includes a PDTS pin which tri-states the  
output clocks and powers down the entire chip.  
The ICS307-02 features a default clock output at  
start-up and is recommended for all new designs.  
Very low jitter  
Operating voltage of 3.3 V or 5 V  
25 mA drive capability at TTL levels  
Industrial temperature version available  
NOTE: EOL for non-green parts to occur on 5/13/10  
per PDN U-09-01  
This product is intended for clock generation. It has low  
output jitter (variation in the output period), but input to  
output skew and jitter are not defined nor guaranteed.  
For applications which require defined input to output  
skew, use the ICS527-01.  
Block Diagram  
VDD  
TTL  
V8:V0  
9
2
3
2
SCLK  
DATA  
C1:C0  
S2:S0  
F1:F0  
Shift  
Register  
STROBE  
VCO  
Divider  
7
R6:R7  
CLK1  
X1/ICLK  
Phase Comparator,  
Charge Pump, and  
Loop Filter  
Crystal  
Oscillator  
Reference  
Divider  
Output  
Divider  
VCO  
PDTS  
CLK2  
Crystal or  
clock input  
Function  
Select  
X2  
3
3
Optional crystal capacitors  
S2:S0  
F1:F0  
GND  
IDT™ / ICS™ SERIALLY PROGRAMMABLE CLOCK SOURCE  
1
ICS307-01/-02 REV H 090209  

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