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291PGILF

更新时间: 2024-01-27 03:20:42
品牌 Logo 应用领域
艾迪悌 - IDT 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
10页 222K
描述
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER

291PGILF 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:0.173 INCH, TSSOP-20
针数:20Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.06JESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:6.5 mm
湿度敏感等级:1端子数量:20
最高工作温度:70 °C最低工作温度:
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
主时钟/晶体标称频率:166 MHz认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

291PGILF 数据手册

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DATASHEET  
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER ICS291  
Description  
Features  
The ICS291 field programmable spread spectrum clock  
synthesizer generates up to six high-quality, high-frequency  
clock outputs including multiple reference clocks from a  
low-frequency crystal input. It is designed to replace  
crystals, crystal oscillators and stand alone spread  
spectrum devices in most electronic systems.  
Packaged as 20-pin TSSOP – Pb-free, RoHS compliant  
Eight addressable registers  
Replaces multiple crystals and oscillators  
Output frequencies up to 200 MHz at 3.3 V  
Configurable Spread Spectrum Modulation  
Input crystal frequency of 5 to 27 MHz  
Clock input frequency of 3 to 166 MHz  
Up to six reference outputs  
TM  
Using IDT’s VersaClock software to configure PLLs and  
outputs, the ICS291 contains a One-Time Programmable  
(OTP) ROM for field programmability. Programming  
features include input/output frequencies, spread spectrum  
amount, eight selectable configuration registers and up to  
two sets of three low-skew outputs.  
Separate 1.8 to 3.3 V VDDO output level controls for  
each bank of 3 outputs  
Up to two sets of three low-skew outputs  
Operating voltages of 3.3 V  
Controllable output drive levels  
Advanced, low-power CMOS process  
Each of the two output groups are powered by a separate  
VDDO voltage. VDDO may vary from 1.8 V to VDD.  
Using Phase-Locked Loop (PLL) techniques, the device  
runs from a standard fundamental mode, inexpensive  
crystal, or clock. It can replace multiple crystals and  
oscillators, saving board space and cost.  
The ICS291 is also available in factory programmed custom  
versions for high-volume applications.  
Block Diagram  
VDDO1  
3
VDD  
PLL1 with  
Spread  
Spectrum  
3
S2:S0  
OTP  
CLK1  
CLK2  
CLK3  
ROM  
with PLL  
Values  
Divide  
Logic  
and  
Output  
Enable  
Control  
PLL2  
PLL3  
CLK4  
CLK5  
CLK6  
X1/ICLK  
Crystal  
Oscillator  
Crystal or  
Clock Input  
X2  
3
External capacitors  
are required with a crystal input.  
GND  
VDDO2  
PDTS  
IDT™ / ICS™ TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER 1  
ICS291  
REV F 051310  

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