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251PMLFT

更新时间: 2024-02-08 12:22:07
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路晶体
页数 文件大小 规格书
10页 138K
描述
Clock Generator, 200MHz, CMOS, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8

251PMLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm湿度敏感等级:1
端子数量:8最高工作温度:70 °C
最低工作温度:最大输出时钟频率:200 MHz
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:150 MHz
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Clock Generators最大供电电压:3.45 V
最小供电电压:3.15 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

251PMLFT 数据手册

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Field Programmable SS VersaClock®  
Synthesizer  
ICS251  
DATASHEET  
Description  
Features  
The ICS251 is a low cost, single-output, field programmable  
clock synthesizer. The ICS251 can generate an output  
frequency from 314kHz to 200MHz and may employ Spread  
Spectrum techniques to reduce system electro-magnetic  
interference (EMI).  
8-pin SOIC package  
Four addressable registers  
Input crystal frequency of 5 to 27MHz  
Clock input frequency of 3 to 150MHz  
Output clock frequencies up to 200MHz  
Configurable spread spectrum modulation  
Operating voltage of 3.3V  
Using IDT’s VersaClock software to configure the PLL and  
output, the ICS251 contains a One-Time Programmable  
(OTP) ROM to allow field programmability. Programming  
features include 4 selectable configuration registers.  
Replaces multiple crystals and oscillators  
Controllable output drive levels  
Advanced, low-power CMOS process  
RoHS compliant packaging  
The device employs Phase-Locked Loop (PLL) techniques to  
run from a standard fundamental mode, inexpensive crystal,  
or clock. It can replace multiple crystals and oscillators,  
saving board space and cost.  
The device also has a power-down feature that tri-states the  
clock outputs and turns off the PLLs when the PDTS pin is  
taken low.  
The ICS251 is also available in factory programmed custom  
versions for high-volume applications.  
Block Diagram  
VDD  
OTP ROM  
2
with PLL  
S1:0  
Divider  
Values  
PLL Clock Synthesis,  
Spread Spectrum and  
Control Circuitry  
CLK  
Crystal or  
clock input  
X1/ICLK  
Crystal  
Oscillator  
X2  
GND  
External capacitors are  
required with a crystal input.  
PDTS (output and PLL)  
ICS251 OCTOBER 10, 2017  
1
©2017 Integrated Device Technology, Inc.  

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