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2510CG-T PDF预览

2510CG-T

更新时间: 2024-02-19 22:19:49
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
7页 81K
描述
PLL Based Clock Driver, 2510 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 MM, 0.65 MM PITCH, PLASTIC, MO-153, TSSOP-24

2510CG-T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP24,.25针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.06系列:2510
输入调节:STANDARDJESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:7.8 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER最大I(ol):0.008 A
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:24
实输出次数:10最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP24,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.15 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

2510CG-T 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS2510C  
3.3V Phase-Lock Loop Clock Driver  
General Description  
Features  
The ICS2510C is a high performance, low skew, low jitter  
clock driver.It uses a phase lock loop (PLL) technology to  
align, in both phase and frequency, the CLKIN signal with  
the CLKOUT signal.It is specifically designed for use with  
synchronous SDRAMs.The ICS2510C operates at 3.3V  
VCC and drives up to ten clock loads.  
Meets or exceeds PC133 registered DIMM  
specification1.1  
Spread Spectrum Clock Compatible  
Distributes one clock input to one bank of ten outputs  
Operating frequency 25MHz to 175MHz  
External feedback input (FBIN) terminal is used to  
synchrionize the outputs to the clock input  
No external RC network required  
Operates at 3.3V Vcc  
Plastic 24-pin 173mil TSSOP package  
One bank of ten outputs provide low-skew, low-jitter  
copies of CLKIN. Output signal duty cycles are adjusted  
to 50 percent, independent of the duty cycle at CLKIN.  
Outputs can be enabled or disabled via control (OE)  
inputs. When the OE inputs are high, the outputs align in  
phaseandfrequencywithCLKIN;whentheOEinputsare  
low, the outputs are disabled to the logic low state.  
The ICS2510C does not require external RC filter  
components.TheloopfilterforthePLLisincludedon-chip,  
minimizing component count, board space, and cost.The  
test mode shuts off the PLL and connects the input  
directlytotheoutputbuffer.Thistestmode, theICS2510C  
can be use as low skew fanout clock buffer device. The  
ICS2510C comes in 24 pin 173mil Thin Shrink Small-  
Outline package (TSSOP) package.  
Pin Configuration  
Block Diagram  
FBOUT  
CLK0  
AGND  
VCC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CLKIN  
AVCC  
VCC  
2
CLK1  
CLK0  
CLK1  
CLK2  
GND  
3
4
CLK9  
CLK8  
GND  
GND  
CLK7  
CLK6  
CLK5  
VCC  
CLK2  
FBIN  
5
PLL  
CLK3  
CLK4  
6
CLKIN  
AVCC  
GND  
7
CLK3  
CLK4  
VCC  
8
CLK5  
CLK6  
CLK7  
9
10  
11  
12  
OE  
FBOUT  
FBIN  
CLK8  
CLK9  
24 Pin TSSOP  
4.40 mm. Body, 0.65 mm. pitch  
OE  
0010G09/22/09  

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