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2509CYG-T PDF预览

2509CYG-T

更新时间: 2024-02-24 08:36:41
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 251K
描述
PLL Based Clock Driver, 2509 Series, 9 True Output(s), 0 Inverted Output(s), PDSO24, 4.40 MM, 0.65 MM PITCH, PLASTIC, MO-153, TSSOP-24

2509CYG-T 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:4.40 MM, 0.65 MM PITCH, PLASTIC, MO-153, TSSOP-24针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.64系列:2509
输入调节:STANDARDJESD-30 代码:R-PDSO-G24
JESD-609代码:e0长度:7.8 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:24实输出次数:9
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.15 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:4.4 mmBase Number Matches:1

2509CYG-T 数据手册

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DATA SHEET  
ICS2509C  
3.3V Phase-Lock Loop Clock Driver  
General Description  
Features  
The ICS2509C is a high performance, low skew, low jitter  
clock driver.It uses a phase lock loop (PLL) technology to  
align, in both phase and frequency, the CLKIN signal with  
the CLKOUT signal.It is specifically designed for use with  
synchronous SDRAMs.The ICS2509C operates at 3.3V  
VCC and drives up to nine clock loads.  
Meets or exceeds PC133 registered DIMM  
specification 1.1  
Spread Spectrum Clock Compatible  
Distributes one clock input to one bank of five and one  
bank of four outputs  
Separate output enable(OEA,OEB) for each output  
bank  
Operating frequency 25 MHz to 175 Mhz  
External feedback input (FBIN) terminal is used to  
synchrionize the outputs to the clock input  
No external RC network required  
Operates at 3.3V Vcc  
Plastic 24-pin 173mil TSSOP package  
One bank of five outputs and one bank of four outputs  
provide nine low-skew, low-jitter copies of CLKIN.Output  
signaldutycyclesareadjustedto50percent, independent  
of the duty cycle at CLKIN. Each bank of outputs can be  
enabledordisabledseparatelyviacontrol(OEAandOEB)  
inputs. When the OE inputs are high, the outputs align in  
phaseandfrequencywithCLKIN;whentheOEinputsare  
low, the outputs are disabled to the logic low state.  
The ICS2509C does not require external RC filter  
components.TheloopfilterforthePLLisincludedon-chip,  
minimizing component count, board space, and cost.The  
buffer mode shuts off the PLL and connects the input  
directlytotheoutputbuffer.Thisbuffermode,theICS2509C  
can be use as low skew fanout clock buffer device. The  
ICS2509C comes in 24 pin 173mil Thin Shrink Small-  
Outline package (TSSOP) package.  
Block Diagram  
Pin Configuration  
AGND  
VCC  
CLKA0  
CLKA1  
CLKA2  
GND  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CLKIN  
AVCC  
VCC  
CLKB0  
CLKB1  
GND  
FBOUT  
CLKA0  
CLKA1  
FBIN  
GND  
GND  
PLL  
CLKA2  
CLKA3  
CLKA4  
CLKB0  
CLKB1  
CLKB2  
CLKB3  
CLKIN  
CLKA3  
CLKA4  
VCC  
OEA  
FBOUT  
CLKB2  
CLKB3  
VCC  
OEB  
FBIN  
10  
11  
12  
AVCC  
OEA  
24 Pin TSSOP  
4.40 mm. Body, 0.65 mm. pitch  
OEB  
IDT™ / ICS™ 3.3V Phase-Lock Loop Clock Driver  
ICS2509C  
1

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